Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract: To fix hold time violations, timing analysis is initially performed on a circuit design for each set of timing constraints to determine a setup slack and a hold slack for each signal path for that set of timing constraints. The slack for a signal path indicates the amount of timing margin or the amount of timing violation for that signal path. Signal paths with hold time violations (or “hold paths”) are identified and retained, and other signal paths without hold time violations are discarded. For each hold path, signal paths with at least one node in common with the hold path (or “related setup paths”) are identified and retained. Related setup paths with large setup slacks may be pruned. The hold time violations for the hold paths are then fixed based on the hold slacks for the hold paths and the setup slacks for the related setup paths.

Abstract: An electrical feedback fashion brake arrester is provided with a motor movement automatic detecting and differentiating device that is mounted in the control loop of the electrical feedback fashion brake arrester. The motor movement automatic detecting and differentiating device receives the existing stroke position feedback signal, determines whether the brake members are in locking configuration, and determines whether the duty cycle and the current of the driving motor should be limited. Hence, the current that is output when the motor is at rest does not exceed that of the maximum sustainable torque force so that the electrical arrester is prevented from being damaged.

Abstract: A customizable instruction-set processor (10) implements complex, time-consuming operations by reconfiguring a portion of an instruction execution unit (34) to perform a group of specific functions in hardware rather than implementing a string of operations in software routines. The instruction execution unit (34) has a non-programmable section (46) and a programmable section (48) that receive an opcode and output control signals for controlling a datapath (16). The datapath (16) has a non-programmable datapath (18) and a programmable datapath (32). The programmable section (48) and the programmable datapath (32) are programmed by the user to provide a customizable instruction-set that controls and adds functionality to the customizable instruction-set processor (10).

Abstract: A computer implemented architectural design method for designing an integrated circuit. An algorithmic description of the behavior of the integrated circuit is created (step 202), from which a register transfer logic (RTL) implementation (400, 500) of the integrated circuit is generated by performing a set of design tasks (steps 204-212). The RTL implementation is modified after performing one of the design tasks by branching to another design task such that the design tasks are performed in any order. Data is stored in a common database (12) which can be edited interactively through one of a plurality of data editors (14-22).

Abstract: A method (30) and apparatus (300) for characterizing the operation of an architectural system designed through a plurality of design tasks (102-112). The design tasks are associated with architectural design rules (114-124) that compare a mapping of the system to a set of rules which are indicative of an error-free system. Objects in the mapping that do not conform to the architectural rules are identified and can be displayed at multiple architectural levels through one or more editors (26-28) and modified without leaving the editors. The system is dynamically characterized by annotating an RTL component (step 153) and simulating the system over a range of simulation cycles. The annotated component (130) monitors states of the system for storing in an analysis database (24). States at selectable simulation cycles are displayed in different orders and at multiple architectural levels.

Abstract: A controller structure template (60) and method (10) of using the controller structure template (60) for designing a controller structure is provided. The method includes providing (11) a behavioral specification, scheduling, allocating, and binding the behavioral specification (12), dividing (13) the list of statements into statement blocks, clustering (14) the list of statements from each statement block, mapping (15) each statement block into a control block, and mapping (17) each cluster into a control element. The steps of mapping (15 and 17) are performed using a controller structure template (60), which includes a control element template (62), merging logic circuit (63), detection circuit (64), branching logic (67).