Patents by Inventor Chii Guang Lee

Chii Guang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735022
    Abstract: An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 ?m. All nanowires of the plurality of nanowires are substantially parallel to each other.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: August 15, 2017
    Assignee: ALPHABET ENERGY, INC.
    Inventors: Mingqiang Yi, Matthew L. Scullin, Gabriel Matus, Dawn L. Hilken, Chii Guang Lee, Sylvain Muckenhirn
  • Patent number: 9514931
    Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: December 6, 2016
    Assignee: Alphabet Energy, Inc.
    Inventors: Mingqiang Yi, Gabriel A. Matus, Matthew L. Scullin, Chii Guang Lee, Sylvain Muckenhirn
  • Patent number: 9240328
    Abstract: An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 ?m. All nanowires of the plurality of nanowires are substantially parallel to each other.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: January 19, 2016
    Assignee: Alphabet Energy, Inc.
    Inventors: Mingqiang Yi, Matthew L. Scullin, Gabriel Alejandro Matus, Dawn L. Hilken, Chii Guang Lee, Sylvain Muckenhirn
  • Publication number: 20150093904
    Abstract: An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 ?m. All nanowires of the plurality of nanowires are substantially parallel to each other.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Inventors: Mingqiang YI, Matthew L. SCULLIN, Gabriel MATUS, Dawn L. HILKEN, Chii Guang LEE, Sylvain MUCKENHIRN
  • Publication number: 20140193982
    Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 10, 2014
    Applicant: Alphabet Energy, Inc.
    Inventors: Mingqiang Yi, Gabriel A. Matus, Matthew L. Scullin, Chii Guang Lee, Sylvain Muckenhirn
  • Patent number: 8736011
    Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: May 27, 2014
    Assignee: Alphabet Energy, Inc.
    Inventors: Mingqiang Yi, Gabriel A. Matus, Matthew L. Scullin, Chii Guang Lee, Sylvain Muckenhirn
  • Publication number: 20130175654
    Abstract: Array of nanoholes and method for making the same. The array of nanoholes includes a plurality of nanoholes. Each of the plurality of nanoholes corresponds to a first end and a second end, and the first end and the second end are separated by a first distance of at least 100 ?m. Each of the plurality of nanoholes corresponds to a cross-sectional area associated with a distance across, and the distance across ranges from 5 nm to 500 nm. Each of the plurality of nanoholes is separated from at least another nanohole selected from the plurality of nanoholes by a semiconductor material associated with a sidewall thickness, and the sidewall thickness ranges from 5 nm to 500 nm.
    Type: Application
    Filed: February 6, 2013
    Publication date: July 11, 2013
    Inventors: Sylvain Muckenhirn, Chii Guang Lee, Matthew L. Scullin
  • Publication number: 20120319082
    Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.
    Type: Application
    Filed: December 1, 2011
    Publication date: December 20, 2012
    Applicant: Alphabet Energy, Inc.
    Inventors: Mingqiang Yi, Gabriel A. Matus, Matthew L. Scullin, Chii Guang Lee, Sylvain Muckenhirn
  • Publication number: 20120295074
    Abstract: An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 ?m. All nanowires of the plurality of nanowires are substantially parallel to each other.
    Type: Application
    Filed: November 17, 2011
    Publication date: November 22, 2012
    Applicant: Alphabet Energy, Inc.
    Inventors: Mingqiang Yi, Matthew L. Scullin, Gabriel Alejandro Matus, Dawn L. Hilken, Chii Guang Lee, Sylvain Muckenhirn
  • Patent number: 7884021
    Abstract: A method for fabricating a micro structure includes disposing a sacrificial material in a recess formed in a lower layer and forming a layer of compensatory material on the sacrificial material in the recess. The compensatory material is higher than the upper surface of the lower layer. A first portion of the compensatory material is removed to form a substantially flat surface on the sacrificial material. The substantially flat surface is substantially co-planar with the upper surface of the lower layer. An upper layer is formed on the lower layer and the substantially flat surface.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: February 8, 2011
    Assignee: Spartial Photonics, Inc.
    Inventors: Shaoher X. Pan, Chii Guang Lee
  • Patent number: 7821010
    Abstract: A method of fabricating a micro structure includes depositing amorphous silicon over a substrate having an electric circuit at a temperature below 550° C. to form a first structure portion, wherein at least part of the first structure portion is configured to receive an electrical signal from the electric circuit.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: October 26, 2010
    Assignee: Spatial Photonics, Inc.
    Inventors: Shaoher X. Pan, Chii Guang Lee
  • Patent number: 7428092
    Abstract: A spatial light modulator includes a mirror plate comprising a reflective upper surface, a lower surface having a conductive surface portion, and a substrate portion having a first cavity having an opening on the lower surface, a second cavity in the substrate portion, and a membrane over the second cavity. The modulator includes a substrate comprising an upper surface, a hinge support post in connection with the upper surface, a hinge component supported by the hinge support post and in connection with the mirror plate to facilitate a rotation of the mirror plate, and an upright landing tip in connection with the upper surface of the substrate. The hinge component is extends into the first cavity. The upright landing tip is configured to contact the membrane over the second cavity in the substrate portion of the mirror plate to stop the rotation of the mirror plate at a predetermined orientation.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: September 23, 2008
    Assignee: Spatial Photonics, Inc.
    Inventors: Chii Guang Lee, Chun-Teh Kao, Hung Kwei Hu, Shaoher X. Pan
  • Publication number: 20080203054
    Abstract: A method for fabricating a micro structure includes disposing a sacrificial material in a recess formed in a lower layer and forming a layer of compensatory material on the sacrificial material in the recess. The compensatory material is higher than the upper surface of the lower layer. A first portion of the compensatory material is removed to form a substantially flat surface on the sacrificial material. The substantially flat surface is substantially co-planar with the upper surface of the lower layer. An upper layer is formed on the lower layer and the substantially flat surface.
    Type: Application
    Filed: February 27, 2007
    Publication date: August 28, 2008
    Applicant: SPATIAL PHOTONICS, INC.
    Inventors: Shaoher X. Pan, Chii Guang Lee
  • Patent number: 7416908
    Abstract: A method for fabricating a micro structure includes depositing a first layer of a first material over a substrate; patterning a first hard mask over the first layer; depositing a second layer of a second material over the first layer and the first hard mask; patterning a second hard mask over the second layer; and selectively removing the first material and the second material not covered by any of the first mask and the second mask to produce over the substrate the micro structure having a first structure portion having a first height and a second structure portion having a second height.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: August 26, 2008
    Assignee: Spatial Photonics, Inc.
    Inventors: Chii Guang Lee, Shaoher X. Pan, Hung Kwei Hu
  • Patent number: 6189484
    Abstract: A helicon wave, high density RF plasma reactor having improved plasma and contaminant control. The reactor contains a well defined anode electrode that is heated above a polymer condensation temperature to ensure that deposits of material that would otherwise alter the ground plane characteristics do not form on the anode. The reactor also contains a magnetic bucket for axially confining the plasma in the chamber using a plurality of vertically oriented magnetic strips or horizontally oriented magnetic toroids that circumscribe the chamber. The reactor may utilize a temperature control system to maintain a constant temperature on the surface of the chamber.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: February 20, 2001
    Assignee: Applied Materials Inc.
    Inventors: Gerald Zheyao Yin, Chii Guang Lee, Arnold Kholodenko, Peter K. Loewenhardt, Hongching Shan, Diana Xiaobing Ma, Dan Katz