Abstract: An embodiment of the invention provides a communication apparatus comprising a radio transceiver and a modem processor. The radio transceiver is configured to transmit or receive wireless signals in a wireless network. The modem processor is coupled to the radio transceiver and configured to perform operations comprising: dividing a tracking reference signal (TRS) set into a plurality of TRS subsets; scheduling a first part of the plurality of TRS subsets for a beam management; and scheduling a second part of the plurality of TRS subsets for a synchronization.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract: A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract: A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.

Abstract: A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency.

Abstract: A method for measuring mismatches in a digitally-controlled oscillator (DCO) includes: in a first settling phase, controlling a first capacitor array of the DCO to have a first capacitive value consistently, and controlling a second capacitor array of the DCO in a closed loop to make a frequency of the DCO locked to a target value; in a second settling phase, controlling the first capacitor array to consistently have a second capacitive value different from the first capacitive value, and controlling the second capacitor array in the closed loop to make the frequency of the DCO locked to the target value; and deriving an estimation from a difference value between a first characteristic value and a second characteristic value, wherein the first and second characteristic values are derived from the digital control word; and estimating the mismatches according to at least the estimation value.

Abstract: A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency.

Abstract: A blind adaptive filtering method for receivers of communication systems without need of training sequences, and whose performance is close to that of the non-blind linear minimum mean square error (LMMSE) receivers with training sequences required in practical environments of finite signal-to-noise (SNR) and data length. This algorithm is an iterative batch processing algorithm using cumulant based inverse filter criteria with super-exponential convergence rate and low computational load. The receivers to which the presented algorithm can be applied are (but not limited to) equalizers of conventional time division multiple access (TDMA) digital communication systems, and smart antennas based on space-time processing for wireless communication systems.

Abstract: In the invention, a simple and robust method for clock offset compensation is proposed using an equalizer with time-varying signal windowing for which the timing information needed is obtained by an existing non-data-aided (NDA) timing estimator. Instead of interpolating the received signal, the proposed method compensates clock offset by using a moving signal window for equalizer. Since no interpolation is needed, the timing information required for the proposed method need not be so accurate as required for interpolation methods. Rather than the exact time drift due to clock offset, the proposed method requires only the timing points where the time drift accumulates to a pre-defined threshold. By applying an existing non-data-aided (NDA) timing estimator, the needed timing information can be obtained easily. Moreover, thanks to robustness of the NDA timing estimator, the proposed method is inherently robust and simple in implementation.

Abstract: A signal detection method with high detection probability and low false alarm rate is provided for spread spectrum communication systems. The method includes steps of a) receiving discrete-time input signal, b) converting the input signal into a correlator output signal with finite number of values, c) selecting a maximum value and a minimum value from the magnitude of values, respectively, d) dividing the maximum value by the minimum value for obtaining an enhanced peak value of the correlator output signal, and e) comparing the enhanced peak value of the correlator output signal with a predetermined threshold, wherein the input signal is detected as a spread spectrum signal if the enhanced peak value of the correlator output signal is greater than or equal to the predetermined threshold, whereas the input signal is not detected as a spread spectrum signal if the enhanced peak value of the correlator output signal is less than the predetermined threshold.

Abstract: A blind adaptive filtering method for receivers of communication systems without need of training sequences, and whose performance is close to that of the non-blind linear minimum mean square error (LMMSE) receivers with training sequences required in practical environments of finite signal-to-noise (SNR) and data length. This algorithm is an iterative batch processing algorithm using cumulant based inverse filter criteria with super-exponential convergence rate and low computational load. The receivers to which the presented algorithm can be applied are (but not limited to) equalizers of conventional time division multiple access (TDMA) digital communication systems, and smart antennas based on space-time processing for wireless communication systems.