Patents by Inventor Chii-Horng Li

Chii-Horng Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651309
    Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
  • Publication number: 20200135467
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 30, 2020
    Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen
  • Publication number: 20200111712
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Publication number: 20200111711
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Publication number: 20200105876
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Application
    Filed: August 22, 2019
    Publication date: April 2, 2020
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Publication number: 20200105526
    Abstract: A transistor is provided including a source-drain region, the source-drain region including a first layer wherein a first average silicon content is between about 80% and 100%, a second layer wherein a second average silicon content is between zero and about 90%, the second average silicon content being smaller than the first average silicon content by at least 7%, and the second layer disposed on and adjacent the first layer, a third layer wherein a third average silicon content is between about 80% and 100%, and a fourth layer wherein a fourth average silicon content is between zero and about 90%, the fourth average silicon content being smaller than the third average silicon content by at least 7%, and the fourth layer disposed on and adjacent the third layer.
    Type: Application
    Filed: July 2, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Yun Chin, Tzu-Hsiang Hsu, Yen-Ru Lee, Chii-Horng Li
  • Publication number: 20200098919
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying Hao HSIEH
  • Publication number: 20200075729
    Abstract: A device is manufactured by etching a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Application
    Filed: June 17, 2019
    Publication date: March 5, 2020
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Publication number: 20200052121
    Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
  • Publication number: 20200032415
    Abstract: An IC fabrication system for facilitating improved thermal uniformity includes a chamber within which an IC process is performed on a substrate, a heating mechanism configured to heat the substrate, and a substrate-retaining device configured to retain the substrate in the chamber. The substrate-retaining device includes a contact surface configured to contact an edge of the retained substrate without the substrate-retaining device contacting a circumferential surface of the retained substrate. The substrate-retaining device includes a plurality of contact regions and a plurality of noncontact regions disposed at a perimeter, where the plurality of noncontact regions is interspersed with the plurality of contact regions. Each of the plurality of noncontact regions includes the contact surface.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Tze-Liang Lee, Chii-Horng Li
  • Publication number: 20200035784
    Abstract: A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su, Tzu-Ching Lin
  • Publication number: 20200035831
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
  • Publication number: 20200020784
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Application
    Filed: September 22, 2019
    Publication date: January 16, 2020
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Publication number: 20200006533
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.
    Type: Application
    Filed: April 5, 2019
    Publication date: January 2, 2020
    Inventors: Ji-Yin Tsai, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Yee-Chia Yeo
  • Publication number: 20200006548
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
  • Publication number: 20190393095
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Patent number: 10510607
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Publication number: 20190378920
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
  • Patent number: 10490648
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 10483396
    Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu