Patents by Inventor Chii Shang Hong
Chii Shang Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240395646Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: ApplicationFiled: August 1, 2024Publication date: November 28, 2024Applicant: Infineon Technologies AGInventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
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Patent number: 12094793Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: GrantFiled: October 16, 2023Date of Patent: September 17, 2024Assignee: Infineon Technologies AGInventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
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Patent number: 12080625Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.Type: GrantFiled: August 18, 2023Date of Patent: September 3, 2024Assignee: Infineon Technologies Austria AGInventors: Li Fong Chong, Yee Beng Daryl Yeow, Chii Shang Hong, Azlina Kassim, Hui Kin Lit
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Publication number: 20240145340Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventors: Jayaganasan Narayanasamy, Angel Enverge, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
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Patent number: 11942383Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.Type: GrantFiled: October 14, 2021Date of Patent: March 26, 2024Assignee: Infineon Technologies AGInventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Ralf Otremba, Daniel Pedone, Bernd Schmoelzer
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Patent number: 11908771Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.Type: GrantFiled: November 12, 2021Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
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Publication number: 20240038612Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: ApplicationFiled: October 16, 2023Publication date: February 1, 2024Applicant: Infineon Technologies AGInventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
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Patent number: 11876028Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: GrantFiled: October 15, 2021Date of Patent: January 16, 2024Assignee: Infineon Technologies AGInventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
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Publication number: 20230361009Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.Type: ApplicationFiled: May 9, 2023Publication date: November 9, 2023Applicant: Infineon Technologies AGInventors: Lee Shuang WANG, Marta ALOMAR DOMINGUEZ, Marcus BÖHM, Edward FÜRGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER
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Patent number: 11804424Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.Type: GrantFiled: December 1, 2020Date of Patent: October 31, 2023Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
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Patent number: 11791238Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.Type: GrantFiled: June 23, 2021Date of Patent: October 17, 2023Assignee: Infineon Technologies Austria AGInventors: Li Fong Chong, Yee Beng Daryl Yeow, Chii Shang Hong, Azlina Kassim, Hui Kin Lit
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Publication number: 20230298956Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.Type: ApplicationFiled: March 8, 2023Publication date: September 21, 2023Applicant: Infineon Technologies AGInventors: Chii Shang HONG, Li Fong CHONG, Yee Beng DARYL YEOW, Edward FÜRGUT, Mei Fen HIEW, Azlina KASSIM, Ralf OTREMBA, Bernd SCHMOELZER, Joon Shyan TAN, Lee Shuang WANG
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Publication number: 20230154827Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.Type: ApplicationFiled: November 12, 2021Publication date: May 18, 2023Inventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
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Publication number: 20220415753Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventors: Li Fong Chong, Yee Beng Daryl Yeow, Chii Shang Hong, Azlina Kassim, Hui Kin Lit
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Publication number: 20220157682Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: ApplicationFiled: October 15, 2021Publication date: May 19, 2022Applicant: Infineon Technologies AGInventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
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Publication number: 20220148934Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.Type: ApplicationFiled: October 14, 2021Publication date: May 12, 2022Applicant: Infineon Technologies AGInventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Ralf Otremba, Daniel Pedone, Bernd Schmoelzer
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Patent number: 11289436Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.Type: GrantFiled: May 28, 2020Date of Patent: March 29, 2022Assignee: Infineon Technologies Austria AGInventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
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Patent number: 11075185Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.Type: GrantFiled: September 18, 2019Date of Patent: July 27, 2021Assignee: Infineon Technologies AGInventors: Chii Shang Hong, Ivan Nikitin, Wei Han Koo, Chiew Li Tai
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Publication number: 20210175157Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.Type: ApplicationFiled: December 1, 2020Publication date: June 10, 2021Inventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
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Patent number: 10978380Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.Type: GrantFiled: May 3, 2019Date of Patent: April 13, 2021Assignee: Infineon Technologies AGInventors: Chii Shang Hong, Wei Han Koo, Chiew Li Tai