Patents by Inventor Chii Shang Hong

Chii Shang Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157682
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Application
    Filed: October 15, 2021
    Publication date: May 19, 2022
    Applicant: Infineon Technologies AG
    Inventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
  • Publication number: 20220148934
    Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.
    Type: Application
    Filed: October 14, 2021
    Publication date: May 12, 2022
    Applicant: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Ralf Otremba, Daniel Pedone, Bernd Schmoelzer
  • Patent number: 11289436
    Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
  • Patent number: 11075185
    Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 27, 2021
    Assignee: Infineon Technologies AG
    Inventors: Chii Shang Hong, Ivan Nikitin, Wei Han Koo, Chiew Li Tai
  • Publication number: 20210175157
    Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 10, 2021
    Inventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
  • Patent number: 10978380
    Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies AG
    Inventors: Chii Shang Hong, Wei Han Koo, Chiew Li Tai
  • Patent number: 10971436
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
  • Publication number: 20200381380
    Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 3, 2020
    Inventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
  • Patent number: 10840164
    Abstract: A semiconductor device package includes an electrically conductive die pad having a die attach surface and an outer surface. A semiconductor die is mounted on the die attach surface. An encapsulant material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material, and bends towards the lower side of the encapsulant material. A first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: November 17, 2020
    Assignee: Infineon Technologies AG
    Inventors: Chii Shang Hong, Edmund Sales Cabatbat, Lee Shuang Wang
  • Publication number: 20200350238
    Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 5, 2020
    Inventors: Chii Shang Hong, Wei Han Koo, Chiew Li Tai
  • Publication number: 20200350272
    Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.
    Type: Application
    Filed: September 18, 2019
    Publication date: November 5, 2020
    Inventors: Chii Shang Hong, Ivan Nikitin, Wei Han Koo, Chiew Li Tai
  • Publication number: 20200020618
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 16, 2020
    Inventors: Thomas STOEK, Chii Shang HONG, Chiew Li TAI, Edmund Sales CABATBAT
  • Publication number: 20190355643
    Abstract: A semiconductor device package includes an electrically conductive die pad having a die attach surface and an outer surface. A semiconductor die is mounted on the die attach surface. An encapsulant material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material, and bends towards the lower side of the encapsulant material. A first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Inventors: Chii Shang Hong, Edmund Sales Cabatbat, Lee Shuang Wang
  • Patent number: 10354943
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat