Patents by Inventor Chik Patrick Yue
Chik Patrick Yue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11757613Abstract: A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLFINV(s). The VLFINV(s) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a ?3-dB corner frequency of 40 MHz.Type: GrantFiled: May 16, 2022Date of Patent: September 12, 2023Assignee: The Hong Kong University of Science and TechnologyInventors: Chik Patrick Yue, Li Wang
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Publication number: 20220385444Abstract: A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLFINV(s). The VLFINV(S) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a ?3-dB corner frequency of 40 MHz.Type: ApplicationFiled: May 16, 2022Publication date: December 1, 2022Inventors: Chik Patrick YUE, Li WANG
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Patent number: 9917707Abstract: The present disclosure provides adaptive cascaded equalization circuits for frequency spectrum compensation. The cascaded equalization are formed in circuit configurations to achieve configurable roll-up frequency responses to compensate for the loss of signal channels in the wire-line or optical communications, particularly but not exclusively, for the loss of signal trace in the wire-line communications, and photodetectors used in the optical communications. These cascaded equalization circuits include two or more stages of equalizers. The peaking frequencies of each stage are set to be different from each other, so that the overall frequency response characteristic has a unique frequency response with a roll-up slope. The equalization function is automatically tuned by an adaptive feedback control loop.Type: GrantFiled: September 9, 2015Date of Patent: March 13, 2018Assignee: The Hong Kong University of Science and TechnologyInventors: Quan Pan, Chik Patrick Yue
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Patent number: 9560722Abstract: A lighting device is provided. The lighting device includes a substrate, integrated circuits (22?, 24), embedded passive components (26, 27), and a lighting component (22), the device being arranged in an architecture having three layers: an integrated circuits layer (11) including the integrated circuits (22?, 24), wherein the integrated circuits layer (11) is integrated on a first side of the substrate; an embedded passive components layer (12) including the embedded passive components (26, 27), wherein the embedded passive components (26, 27) are embedded in grooves formed in the substrate and wherein the embedded passive components are connected to the integrated circuits (22?, 24) through vias (28) in the substrate; and a bonded layer (13), including the lighting component (22), the lighting component (22) being connected to the integrated circuit layer (11) through flip-chip bonding or monolithic integration.Type: GrantFiled: March 25, 2014Date of Patent: January 31, 2017Assignee: The Hong Kong University of Science and TechnologyInventors: Chik Patrick Yue, Johnny Kin On Sin, Kei May Lau
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Publication number: 20160352422Abstract: A communications device includes: a light-emitting diode (LED) or LED array; an internet protocol (IP)-based radiofrequency (RF) wireless unit, configured to transmit and receive data over a RF wireless communications network; a visible light communication (VLC) unit, configured to drive the LED or LED array and modulate light generated by the LED or LED array with data; a control unit, connected to the IP-based RF wireless unit and the VLC unit, configured to facilitate communications between the VLC unit and IP-based RF wireless unit.Type: ApplicationFiled: November 5, 2014Publication date: December 1, 2016Applicant: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Chik Patrick YUE, Liang WU
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Publication number: 20160323968Abstract: A lighting device is provided. The lighting device includes a substrate, integrated circuits (22?, 24), embedded passive components (26, 27), and a lighting component (22), the device being arranged in an architecture having three layers: an integrated circuits layer (11) including the integrated circuits (22?, 24), wherein the integrated circuits layer (11) is integrated on a first side of the substrate; an embedded passive components layer (12) including the embedded passive components (26, 27), wherein the embedded passive components (26, 27) are embedded in grooves formed in the substrate and wherein the embedded passive components are connected to the integrated circuits (22?, 24) through vias (28) in the substrate; and a bonded layer (13), including the lighting component (22), the lighting component (22) being connected to the integrated circuit layer (11) through flip-chip bonding or monolithic integration.Type: ApplicationFiled: March 25, 2014Publication date: November 3, 2016Inventors: Chik Patrick YUE, Johnny Kin On SIN, Kei May LAU
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Publication number: 20160080177Abstract: The present disclosure provides adaptive cascaded equalization circuits for frequency spectrum compensation. The cascaded equalization are formed in circuit configurations to achieve configurable roll-up frequency responses to compensate for the loss of signal channels in the wire-line or optical communications, particularly but not exclusively, for the loss of signal trace in the wire-line communications, and photodetectors used in the optical communications. These cascaded equalization circuits include two or more stages of equalizers. The peaking frequencies of each stage are set to be different from each other, so that the overall frequency response characteristic has a unique frequency response with a roll-up slope. The equalization function is automatically tuned by an adaptive feedback control loop.Type: ApplicationFiled: September 9, 2015Publication date: March 17, 2016Inventors: Quan Pan, Chik Patrick Yue
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Patent number: 7325180Abstract: A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on an otherwise unusable portion of the wafer. The antenna system maybe formed in at least one of the same scribe line as the transceiver or in at least one other scribe line formed in the wafer. Alternatively, the antenna system may include an antenna external to the wafer.Type: GrantFiled: November 26, 2003Date of Patent: January 29, 2008Assignee: Carnegie Mellon UniversityInventors: Lawrence Pileggi, Chik Patrick Yue, R. Shawn Blanton, Thomas Vogels
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Patent number: 6779261Abstract: A method for producing an on-chip signal transforming device. The method includes providing a substrate, and laying a first conductive layer above the substrate, wherein the first conductive layer has a plurality of interleaved inductors. The method then includes laying a second conductive layer above the substrate, wherein the second conductive layer has at least one inductor.Type: GrantFiled: January 15, 2003Date of Patent: August 24, 2004Assignee: Atheros Communications, Inc.Inventor: Chik Patrick Yue
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Patent number: 6731176Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.Type: GrantFiled: March 13, 2002Date of Patent: May 4, 2004Assignee: Atheros Communications, Inc.Inventors: David K. Su, Chik Patrick Yue, David J. Weber, Masound Zargari
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Patent number: 6717502Abstract: An on-chip signal transforming device includes a substrate and a first conductive layer above the substrate, wherein the first conductive layer has a plurality of interleaved inductors. The device further includes a second conductive layer above the substrate, wherein the second conductive layer has at least one inductor.Type: GrantFiled: November 5, 2001Date of Patent: April 6, 2004Assignee: Atheros Communications, Inc.Inventor: Chik Patrick Yue
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Publication number: 20030151881Abstract: A method for producing an on-chip signal transforming device. The method includes providing a substrate, and laying a first conductive layer above the substrate, wherein the first conductive layer has a plurality of interleaved inductors. The method then includes laying a second conductive layer above the substrate, wherein the second conductive layer has at least one inductor.Type: ApplicationFiled: January 15, 2003Publication date: August 14, 2003Inventor: Chik Patrick Yue
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Patent number: 6597227Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.Type: GrantFiled: January 21, 2000Date of Patent: July 22, 2003Assignee: Atheros Communications, Inc.Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
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Patent number: 6593794Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.Type: GrantFiled: February 7, 2002Date of Patent: July 15, 2003Assignee: Atheros CommunicationsInventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
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Patent number: 6570453Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.Type: GrantFiled: March 13, 2002Date of Patent: May 27, 2003Assignee: Atheros Communications, Inc.Inventors: David K. Su, Chik Patrick Yue, David J. Weber, Masound Zargari
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Publication number: 20030085788Abstract: A method for producing an on-chip signal transforming device. The method includes providing a substrate, and laying a first conductive layer above the substrate, wherein the first conductive layer has a plurality of interleaved inductors. The method then includes aying a second conductive layer above the substrate, wherein the second conductive layer has at least one inductor.Type: ApplicationFiled: November 5, 2001Publication date: May 8, 2003Inventor: Chik Patrick Yue
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Patent number: 6509779Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.Type: GrantFiled: February 7, 2002Date of Patent: January 21, 2003Assignee: Atheros Communications, Inc.Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
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Patent number: 6483188Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.Type: GrantFiled: May 15, 2000Date of Patent: November 19, 2002Assignee: Atheros Communications, Inc.Inventors: Chik Patrick Yue, Masoud Zargari, David Su
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Publication number: 20020125931Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.Type: ApplicationFiled: February 7, 2002Publication date: September 12, 2002Applicant: ATHEROS COMMUNICATIONS, INC.Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
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Publication number: 20020121924Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.Type: ApplicationFiled: February 7, 2002Publication date: September 5, 2002Applicant: ATHEROS COMMUNICATIONS, INC.Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland