Patents by Inventor Chikahiro Deguchi
Chikahiro Deguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9542266Abstract: A semiconductor integrated circuit includes a combinational circuit to output a state value and a parity value, a first parity check circuit to perform a parity check based on the state value and the parity value stored in a first FF circuit and output a first parity error, a second parity check circuit to perform a parity check based on the state value and the parity value stored in a second FF circuit and output a second parity error, and a selector to, when the first parity error is not output but the second parity error is output, output the state value in the first FF circuit to the combinational circuit, and when the first parity error is output but the second parity error is not output, output the state value in the second FF circuit to the combinational circuit.Type: GrantFiled: May 27, 2014Date of Patent: January 10, 2017Assignee: FUJITSU LIMITEDInventors: Chikahiro Deguchi, Yutaka Sekino, Yoshiki Okumura, Hiroaki Watanabe, Naoki Maezawa, Hideyuki Negi
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Publication number: 20140372837Abstract: A semiconductor integrated circuit includes: a first-combinational-circuit to output a state-value depending on an input signal and a parity-value of the state-value which are stored by a first-flip-flop-circuit; a first-parity-check-circuit to perform a parity check based on the state-value and the parity-value and output a first-parity-error; a second-flip-flop-circuit to store the state-value and the parity-value output by the first-combinational-circuit; a second-parity-check-circuit to perform a parity check based on the state-value and the parity-value stored in the second-flip-flop-circuit and output a second-parity-error; and a selector to, when the first-parity-error is not output but the second-parity-error is output, output the state-value stored in the first-flip-flop-circuit to the first-combinational-circuit, and when the first-parity-error is output but the second-parity-error is not output, output the state-value stored in the second-flip-flop-circuit to the first-combinational-circuit, whereiType: ApplicationFiled: May 27, 2014Publication date: December 18, 2014Applicant: FUJITSU LIMITEDInventors: Chikahiro Deguchi, Yutaka SEKINO, Yoshiki OKUMURA, Hiroaki WATANABE, Naoki MAEZAWA, Hideyuki NEGI
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Patent number: 8855242Abstract: A data receiving circuit includes a generating unit that generates multiple clocks with different phases from one another. The data receiving circuit includes multiple acquiring units that acquire data from a received data signal by using different clocks from one another out of the multiple clocks generated by the generating unit. The data receiving circuit includes a determining unit that determines whether the data acquired by the multiple acquiring units are consistent. The data receiving circuit includes a correcting unit that corrects the phases of the multiple clocks in a direction in which data inconsistency does not occur when the determining unit has determined that there is data inconsistent with the other data in the data acquired by the multiple acquiring units.Type: GrantFiled: June 12, 2013Date of Patent: October 7, 2014Assignee: Fujitsu LimitedInventors: Hiroaki Watanabe, Hideyuki Negi, Chikahiro Deguchi, Yutaka Sekino
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Publication number: 20140294015Abstract: A relay device receives packets from an information processing apparatus or a relay device. The relay device updates a value of priority data indicating an accumulated wait time for arbitration contained in each of the received packets according to an elapsed time. The relay device selects a packet to be transmitted according to a result of comparison of the values of the pieces of the priority data contained in the received packets. The relay device transmits the selected packet to another relay device.Type: ApplicationFiled: June 10, 2014Publication date: October 2, 2014Inventors: Yutaka SEKINO, Chikahiro Deguchi, Naoki Maezawa, YOSHIKI OKUMURA, Toshihiro Tomozaki, Hiroaki Watanabe, Hideyuki NEGI
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Publication number: 20140192928Abstract: A transmission system includes a data sending device that sends data at a first speed and a data receiving device that receives, by using a plurality of clocks having different phases, data that has been sent by the sending device at the first speed. The data sending device sends, to the data receiving device, some of the data, which is sent at the first speed, at a second speed that is lower than the first speed. Furthermore, in accordance with determination as to whether the content of the received data sent at the second speed matches a corresponding portion of the data received by using a plurality of clocks, the data receiving device changes the timing at which the data that has been sent at the first speed is received.Type: ApplicationFiled: March 14, 2014Publication date: July 10, 2014Applicant: FUJITSU LIMITEDInventors: Yutaka SEKINO, Naoki Maezawa, YOSHIKI OKUMURA, Chikahiro Deguchi
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Publication number: 20140040684Abstract: A system includes a transmitting device configured to transmit a packet, and a receiving device connected through a switch device to the transmitting device, the receiving device being configured to receive the packet, wherein the switch device includes a first memory storing first expected value information indicative of an expected value of a fixed value region, the fixed value region being a region whose value is determined in advance in a transaction layer packet, and a switch control unit configured to compare a value of the fixed value region of the transaction layer packet received from the transmitting device with the expected value and make an error response to the transmitting device if the value of the fixed value region is different from the expected value.Type: ApplicationFiled: July 11, 2013Publication date: February 6, 2014Applicant: FUJITSU LIMITEDInventors: Toshihiro Tomozaki, Yoshiki Okumura, Yutaka Sekino, Naoki Maezawa, Chikahiro Deguchi, Hiroaki Watanabe, Hideyuki Negi
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Publication number: 20130272454Abstract: A data receiving circuit includes a generating unit that generates multiple clocks with different phases from one another. The data receiving circuit includes multiple acquiring units that acquire data from a received data signal by using different clocks from one another out of the multiple clocks generated by the generating unit. The data receiving circuit includes a determining unit that determines whether the data acquired by the multiple acquiring units are consistent. The data receiving circuit includes a correcting unit that corrects the phases of the multiple clocks in a direction in which data inconsistency does not occur when the determining unit has determined that there is data inconsistent with the other data in the data acquired by the multiple acquiring units.Type: ApplicationFiled: June 12, 2013Publication date: October 17, 2013Inventors: Hiroaki WATANABE, Hideyuki Negi, Chikahiro Deguchi, Yutaka Sekino
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Patent number: 8503259Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.Type: GrantFiled: March 17, 2009Date of Patent: August 6, 2013Assignee: Fujitsu LimitedInventors: Shogo Shibazaki, Shinkichi Gama, Hideyuki Negi, Takeshi Nagase, Chikahiro Deguchi, Yutaka Sekino
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Patent number: 8436644Abstract: A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful.Type: GrantFiled: March 11, 2011Date of Patent: May 7, 2013Assignee: Fujitsu LimitedInventors: Hiroaki Watanabe, Naoki Maezawa, Chikahiro Deguchi
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Patent number: 8143901Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.Type: GrantFiled: February 19, 2009Date of Patent: March 27, 2012Assignee: Fujitsu LimitedInventors: Chikahiro Deguchi, Yutaka Sekino, Shogo Shibazaki, Shinkichi Gama, Takeshi Nagase, Hideyuki Negi
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Publication number: 20110227605Abstract: A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful.Type: ApplicationFiled: March 11, 2011Publication date: September 22, 2011Applicant: FUJITSU LIMITEDInventors: Hiroaki Watanabe, Naoki Maezawa, Chikahiro Deguchi
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Publication number: 20090300443Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.Type: ApplicationFiled: February 19, 2009Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventors: Chikahiro Deguchi, Yutaka Sekino, Shogo Shibazaki, Shinkichi Gama, Takeshi Nagase, Hideyuki Negi
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Publication number: 20090296505Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.Type: ApplicationFiled: March 17, 2009Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventors: Shogo Shibazaki, Shinkichi Gama, Hideyuki Negi, Takeshi Nagase, Chikahiro Deguchi, Yutaka Sekino
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Patent number: 7158638Abstract: An encryption circuit that reduces a scale of circuit and can achieve a certain level of high-speed processing in the implementation of the AES block cipher.Type: GrantFiled: January 3, 2002Date of Patent: January 2, 2007Assignee: Fujitsu LimitedInventors: Souichi Okada, Naoya Torii, Tomohiro Hayashi, Chikahiro Deguchi, Yumi Fujiwara
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Publication number: 20030108195Abstract: An encryption circuit that reduces a scale of circuit and can achieve a certain level of high-speed processing in the implementation of the AES block cipher.Type: ApplicationFiled: January 3, 2002Publication date: June 12, 2003Applicant: Fujitsu LimitedInventors: Souichi Okada, Naoya Torii, Tomohiro Hayashi, Chikahiro Deguchi, Yumi Fujiwara
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Patent number: 5648975Abstract: A method and apparatus for selecting test patterns of a plurality of groups of test patterns for testing parts of an integrated circuit. The plurality of groups of test patterns are applied to the parts of the integrated circuit to determine which parts are detected by the plurality of groups of test patterns. The detected parts form a group of parts. Each of the groups of test patterns is selectively identified as either necessary or unnecessary by repeatedly referring to the group of parts. Each time a respective group of test patterns is determined to be necessary, the group of parts is reduced by the parts detected by the respective group of test patterns determined to be necessary. After each of the groups of test patterns has been identified as either necessary or unnecessary, the unnecessary groups of test patterns are eliminated, to form a set of remaining necessary groups of test patterns for testing the integrated circuit.Type: GrantFiled: February 1, 1996Date of Patent: July 15, 1997Assignee: Fujitsu LimitedInventor: Chikahiro Deguchi