Abstract: According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit.

Abstract: According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit.

Abstract: A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

Abstract: A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

Abstract: A bidirectional buffer circuit includes a first terminal, a second terminal, a first output buffer to which a signal from the first terminal is input and which outputs the signal to the second terminal, a first one-shot buffer control circuit outputting a first control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, a first one-shot buffer temporarily driving the second terminal by the first control signal, a second output buffer to which a signal from the second terminal is input and which outputs the signal to the first terminal, a second one-shot buffer control circuit outputting a second control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, and a second one-shot buffer temporarily driving the first terminal by the second control signal.

Abstract: A bidirectional buffer circuit includes a first terminal, a second terminal, a first output buffer to which a signal from the first terminal is input and which outputs the signal to the second terminal, a first one-shot buffer control circuit outputting a first control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, a first one-shot buffer temporarily driving the second terminal by the first control signal, a second output buffer to which a signal from the second terminal is input and which outputs the signal to the first terminal, a second one-shot buffer control circuit outputting a second control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, and a second one-shot buffer temporarily driving the first terminal by the second control signal.

Abstract: An oscillation circuit comprises a ring oscillator configured to have at least an odd number of stages of inverters, and a frequency multiplier section configured to output as a multiplied output, an exclusive OR of signals taken out from the inverters at least at two stages of the ring oscillator.

Abstract: A differential signal generating circuit has first and second transistors connected in series between a first node and a second node, third and fourth transistors connected in series between the first node and the second node, a first differential output terminal connected to a connection path between the first transistor and the second transistor, a second differential output terminal connected to a connection path between the third transistor and the fourth transistor, and a gate signal generating circuit which generates a first gate signal applied to gate terminals of the first and fourth transistors and a second gate signal applied to gate terminals of the second and third transistors, a timing when a logic of the first gate signal changes being different from a timing when a logic of the second gate signal changes.

Abstract: An output buffer circuit disclosed herein includes a buffer supplied with an input signal and outputting an output signal from an output terminal; a driving assistant buffer including a first MISFET provided at one of a first position and a second position, the first position being between the output terminal and a first power supply and the second position being between the output terminal and a second power supply; a first logic circuit configured to perform a logic operation based on a first logical threshold using the output signal to output a first logic signal; a second logic circuit configured to perform the same logic operation as the first logic circuit based on a second logical threshold using the output signal to output a second logic signal; and a third logic circuit outputting a control signal to control the first MISFET and including second and third MISFETs connected in series, the first logic signal being inputted to a gate of the second MISFET and the second logic signal being inputted to a g

Abstract: An output buffer circuit disclosed herein includes a buffer supplied with an input signal and outputting an output signal from an output terminal; a driving assistant buffer including a first MISFET provided at one of a first position and a second position, the first position being between the output terminal and a first power supply and the second position being between the output terminal and a second power supply; a first logic circuit configured to perform a logic operation based on a first logical threshold using the output signal to output a first logic signal; a second logic circuit configured to perform the same logic operation as the first logic circuit based on a second logical threshold using the output signal to output a second logic signal; and a third logic circuit outputting a control signal to control the first MISFET and including second and third MISFETs connected in series, the first logic signal being inputted to a gate of the second MISFET and the second logic signal being inputted to a g

Abstract: A logic circuit has a signal line for transmitting a digital signal as a voltage level and a loop circuit serving as a memory unit for storing the digital signal. Input and output terminals of the loop circuit are connected to the signal line. The loop circuit is a partial circuit having an even number (at least two) of signal inverters each having capacitive input load. At least one of the input and output terminals of the loop circuit is connected to an electric resistor. The loop circuit has a time constant T that is determined by the product RC of the resistance R of the resistor and the intentional and parasitic capacitance C of the signal inverters. The time constant T has a given relationship with the operation frequency of the logic circuit. The resistance R and capacitance C form a low-pass filter. The logic circuit provides different equivalent circuits in high and low frequency regions above and below the cutoff frequency of the low-pass filter.

Abstract: A priority encoder with two inputs, an exponent input and a mantissa input, forming a floating-point number, wherein the priority encoder outputs the smallest value after comparing the two inputs and the output from the priority encoder is input to a substractor and a barrel shifter. The barrel shifter shifts the mantissa input before the completion of the subtract operation. First, the mantissa input is left-shifted by the left barrel shifter under the selection of the selector controlled by the control signal in accordance with the value of the exponent input. The first result from the barrel shifter is stored in the data holding circuit after shifting it to the right by one bit with the right direction 1-bit shifter. Next, the mantissa input is shifted to the left by the left direction barrel shifter. The second result of the barrel shifter is not stored in the data holding circuit. One of the above two results is selected by the selector.

Abstract: In designing an integrated circuit having a logic circuit area and a clock supplying circuit, the layout of the clock supplying circuit can be designed before the completion of the layout designing of the logic circuit area. Clock buffers and wires that are component elements of the clock supplying circuit are arranged in a peripheral region of the logic circuit area. This arrangement enables the layout designing of the clock supplying circuit to be done with no influence of the layout designing of the logic circuit area.

Abstract: An associative memory device in which a detection or determination is made if the same information as that to be written in the associative memory cells has been stored therein before storing the information to be written in the memory cells, and if the result of the detection is that the same information has been stored therein, the information to be written is inhibited from being stored while when the same information has not been stored therein, the information to be written is permitted to be stored in a predetermined memory cell, so as not to store the same information into a plurality of different addresses of the memory cells.

Abstract: Associative memory cell with low power consumption and capable of performing a high speed operation in which MOS transistors of a first conductive type constituting transfer gates for transferring data between and data hold circuit and bit lines and those of opposite conductive type constituting an data retrieval circuit are used, so that the data stored in the data hold circuit can be read out stably and securely, as well.

Abstract: According to this invention a plurality of kinds of circuit blocks is formed as a circuit block area on a chip substrate to have a desired logic function. An array of signal output wires and array of signal input wires are formed adjacent the circuit block area such that these arrays intersect each other. First switching elements are each formed at a corresponding intersection of the signal output wire and signal input wire. An LSI device having a desired logic function can be implemented by electrically and fixedly writing an ON or OFF state of the first switching element. A first control wire and second control wire are provided adjacent to the circuit block area with the wire arranged parallel to the signal output wire and the wire arranged parallel to the signal input wire. Second switching elements are arranged at intersections of the first control wire and the signal input wires and at intersections of the second control wire and signal output wires.