Patents by Inventor Chikai Ohno

Chikai Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6496428
    Abstract: A redundancy information region having memory cells for retaining relief information indicating the locations of defective memory cells is arranged closer to at least one of a word driver or a plate driver than a memory cell region and a redundancy memory cell region. Since the memory cells of the redundancy information region start operation earlier, a relief/no-relief judgment can be made earlier, allowing reduction in access time. Besides, in memory cell operations, the defective memory cells are deselected in accordance with address information held in a redundancy address region. Redundancy memory cells for relieving the defective memory cells are selected in accordance with the relief information held in a redundancy flag region. Since the redundancy memory cells are selected without using the address information, it is possible to reduce the time that elapses before the redundancy memory cells are selected after the selection of word lines.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: December 17, 2002
    Assignee: Fujitsu Limited
    Inventors: Chikai Ohno, Hirokazu Yamazaki, Hideaki Suzuki
  • Publication number: 20020097618
    Abstract: A redundancy information region having memory cells for retaining relief information indicating the locations of defective memory cells is arranged closer to at least one of a word driver or a plate driver than a memory cell region and a redundancy memory cell region. Since the memory cells of the redundancy information region start operation earlier, a relief/no-relief judgment can be made earlier, allowing reduction in access time. Besides, in memory cell operations, the defective memory cells are deselected in accordance with address information held in a redundancy address region. Redundancy memory cells for relieving the defective memory cells are selected in accordance with the relief information held in a redundancy flag region. Since the redundancy memory cells are selected without using the address information, it is possible to reduce the time that elapses before the redundancy memory cells are selected after the selection of word lines.
    Type: Application
    Filed: September 28, 2001
    Publication date: July 25, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Chikai Ohno, Hirokazu Yamazaki, Hideaki Suzuki
  • Patent number: 4882712
    Abstract: A synchronous semiconductor memory device has a noise preventing part for preventing a noise from being transmitted to a memory cell array, where the noise is caused by a change in a write data.
    Type: Grant
    Filed: September 26, 1988
    Date of Patent: November 21, 1989
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Chikai Ohno, Michiyuki Hirata