Abstract: The disclosed is an improved superscalar processor for reducing the time required for execution of an instruction. The superscalar processor includes an instruction fetching stage, an instruction decoding stage, and function units each having a pipeline structure. A function unit includes an execution stage, a memory access stage, and a write back stage. Function units are connected through a newly provided bypass line. Data obtained by preceding execution in the other function unit (the other pipeline) is applied through the bypass line to a function unit (pipeline) for executing a later instruction. Executed data is transmitted between pipelines without through a register file, so that it becomes unnecessary for the pipeline requesting the executed data to wait for termination of execution of the other pipeline. As a result, time required for execution of an instruction is reduced.

Abstract: The disclosed is an improved superscalar processor for reducing the time required for execution of an instruction. The superscalar processor includes an instruction fetching stage, an instruction decoding stage, and function units each having a pipeline structure. A function unit includes an execution stage, a memory access stage, and a write back stage. Function units are connected through a newly provided bypass line. Data obtained by preceding execution in the other function unit (the other pipeline) is applied through the bypass line to a function unit (pipeline) for executing a later instruction. Executed data is transmitted between pipelines without through a register file, so that it becomes unnecessary for the pipeline requesting the executed data to wait for termination of execution of the other pipeline. As a result, time required for execution of an instruction is reduced.

Abstract: Source operand data supplied from a register file are held in registers. The data of the registers and load data from a data memory are bypassed and supplied to a selection circuit. An execution stage includes an arithmetic and logic unit for performing an operation on the source operand data and a memory access stage includes an arithmetic and logic unit for performing an operation on data selected by the selection circuit. Selection of the selection circuit is controlled by data dependency between a load instruction and an operation instruction following the same. The output of the arithmetic and logic unit in the execution stage and the output of the arithmetic and logic unit in the memory access stage are selected in a selector according to a presence/absence of data dependency. Load data from the data memory is also supplied to the selector.

Abstract: A parallel computer having a boosting function in which an instruction belonging to a later basic block is moved to a precedent basic block in an instruction group, the moved basic block being a branch instruction. The moved instruction and an instruction in the precedent basic block are arranged in parallel in the order of an instruction code. Therefore, the number of boosted instructions which can be executed in parallel is increased and the degree of parallelization of instruction is increased so that the function of the computer is improved.

Abstract: An arithmetic and logic processor includes a register file structure wherein each procedure to be processed has assigned thereto a predetermined number of registers referred to as register window. The processor further includes circuitry for comparing a predetermined constant LENGTH with the difference between the register window currently utilized by a procedure under execution and the base address of the register file, and circuitry responsive to the comparing circuitry output to detect when data should be transferred on a window basis to or from the register file from or to a stack memory for saving the register file contents, and circuitry responsive to the decision circuitry output to perform data transfer between the register file and the stack memory. According to such circuitry, overflow and underflow of the register file can be greatly suppressed to improve processing speed of the processor.

Abstract: An arithmetic and logic processor includes a register file structure wherein each procedure to be processed has assigned thereto a predetermined number of registers referred to as register window. The processor further includes circuitry for comparing a predetermined constant LENGTH with the difference between the register window currently utilized by a procedure under execution and the base address of the register file, and circuitry responsive to the comparing circuitry output to detect when data should be transferred on a window basis to or from the register file from or to a stack memory for saving the register file contents, and circuitry responsive to the decision circuitry output to perform data transfer between the register file and the stack memory. According to such circuitry, overflow and underflow of the register file can be greatly suppressed to improve processing speed of the processor.

Abstract: A bus circuit of a precharging type has an hierarchical structure comprising a higher rank bus and a plurality of lower rank buses connected in parallel thereto. A register block is connected to each of the lower rank buses, each register block comprising a plurality of registers connected in parallel to the lower rank bus. Both of the higher and the lower rank buses are precharged. The data of the register selected as a bus source is read onto the higher rank bus, thereby fluctuating a potential on the higher rank bus. Only the electric charges on the selected lower rank bus are discharged in response to the potential fluctuation and the selection signal. The total number of the registers coupled to the lower rank buses is the power of 2.

Abstract: A bus circuit of a precharging type has an hierarchical structure comprising a higher rank bus and a plurality of lower rank buses connected in parallel thereto. A register block is connected to each of the lower rank buses, each register block comprising a plurality of registers connected in parallel to the lower rank bus. Both of the higher and the lower rank buses are precharged. The data of the register selected as a bus source is read onto the higher rank bus, thereby fluctuating a potential on the higher rank bus. Only the electric charges on the selected lower rank bus are discharged in response to the potential fluctuation and the selection signal. The total number of the registers coupled to the lower rank buses is the power of 2.

Abstract: A bus circuit comprises a bus interconnection (1) and a plurality of local bus interconnections (10). A plurality of circuit blocks (21a to 21d) are connected to each of the plurality of local bus interconnections (10). A multiplexer (70), a bus driver (60) and a transmitting circuit (80A) are provided corresponding to each of the local bus interconnections (10). Each multiplexer (70) selects one of the outputs from the corresponding plurality of circuit blocks (21a to 21d) and applies the selected one to the bus driver (60). The bus driver (60) drives the bus interconnection (1) according to the output of the multiplexer (70). The local bus interconnections (10) are precharged to a predetermined potential in advance. When any of the plurality of transmitting circuits (80A) is selected, the selected transmitting circuit (80A) either discharges the corresponding local bus interconnection (10) or holds the same at a predetermined potential according to the information on the bus interconnection (1).