Patents by Inventor Chikao Makita

Chikao Makita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low impedance semiconductor integrated circuit
    Patent number: 6909569
    Abstract: One circuit generates a constant positive potential, another circuit generates a constant negative potential. The positive potential and the negative potential are applied to a magneto-resistive head that reads data from and writes data to a magnetic disk. The positive potential is generated using a positive voltage source, an operational amplifier, and an NMOS transistor. The negative potential is generated using a negative voltage source, an operational amplifier, and a PMOS transistor.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Chikao Makita, Hideki Miyake
  • Semiconductor device
    Patent number: 6833590
    Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: December 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Chikao Makita, Kunihiko Karasawa
  • Semiconductor device
    Publication number: 20030230781
    Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
    Type: Application
    Filed: March 4, 2003
    Publication date: December 18, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Chikao Makita, Kunihiko Karasawa
  • Low impedance semiconductor integrated circuit
    Publication number: 20030202272
    Abstract: One circuit generates a constant positive potential, other circuit generates a constant negative potential. The positive potential and the negative potential are applied to a magneto-resistive head that reads or writes data from/to a magnetic disk. The positive potential is generated using a positive voltage source, an operational amplifier, and an NMOS transistor. The negative potential is generated using of a negative voltage source, an operational amplifier, and a PMOS transistor.
    Type: Application
    Filed: October 23, 2002
    Publication date: October 30, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Chikao Makita, Hideki Miyake
  • Semiconductor device
    Patent number: 6583475
    Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: June 24, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Chikao Makita, Kunihiko Karasawa
  • Semiconductor device
    Publication number: 20020089018
    Abstract: The NMOS transistor circuit has the surge protection circuit connected in parallel with the NMOS transistor. Resistor is provided between back gate of the NMOS transistor and the ground. As a result, input impedance higher than input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.
    Type: Application
    Filed: June 4, 2001
    Publication date: July 11, 2002
    Inventors: Chikao Makita, Kunihiko Karasawa