Abstract: A plurality of electrically conductive material layers and a plurality of dielectric layers are alternately stacked on a second substrate. The plurality of electrically conductive material layers comprise first and second patterns. The first pattern comprises at least a first pair of overlaying areas free of the electrically conductive material, and the second pattern comprises at least a second pair of overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. The plurality of electrically conductive material layers are electrically isolated from one another by the dielectric layers.

Abstract: A method of assembling a packaged semiconductor device starts by dropping a pre-formed capacitor precursor on a surface of or within a first substrate. An integrated circuit die is dropped on either of the first substrate. If the pre-formed capacitor precursor lacks at least a first pair of vias for providing an electrical contact between capacitor plates of said chip capacitor, then at least a first pair of vias is formed in said pre-formed capacitor precursor. The first pair of vias are filled with an electrically conductive material to form the chip capacitor, wherein said filling of said vias provides an electrical contact between said first and second capacitor plates of said chip capacitor and said electrically conductive contact regions on said first substrate. A plurality of electrically conductive material layers and a plurality of dielectric layers are alternately stacked on a second substrate. The plurality of electrically conductive material layers comprise first and second patterns.

Abstract: A multi-layered integrated circuit chip package comprises a void layer that includes at least one void. The multi-layered integrated circuit chip package also includes an insulation layer that electrically insulates the void layer from a trace layer. At least one trace resides in the trace layer. The trace having a length in which a first section thereof is located an overlying relation to the at least one void, wherein the first section overlying the void has a width different from an adjacent section of the trace located on at least one opposing side of the void such that impedance mismatches and signal reflections along the trace are mitigated.

Abstract: A packaged integrated circuit including a substrate 410 having opposing top and bottom surfaces and a chip 400 having opposing active and bottom surfaces. The chip is mounted on the top surface of the substrate such that the bottom surface of the chip is adjacent to the substrate, and such that the active surface of the chip is away from the substrate. The packaged integrated circuit also includes a thermally-conductive interposer 460 mounted on the active surface of the chip and a heatspreader 470 over the interposer. The interposer can be in contact with or attached to the heatspreader.

Abstract: The purpose of the present invention is to reduce the warpage of the semiconductor package caused by thermal contraction. According to the present invention, semiconductor device (9) has plate-shaped member (7) which is positioned on a surface of semiconductor chip (1) and is sealed together with semiconductor chip (1) with molding resin (8). Said plate-shaped member (7) has a linear expansion coefficient that is less than the linear expansion coefficient of the aforementioned molding resin. By placing a plate-shaped member with a small linear expansion coefficient on semiconductor chip (1), it is possible to reduce the thermal contraction on the upper side of the semiconductor chip. Also, the presence of the plate-shaped member on the semiconductor chip leads to substantial reduction in the thickness of the molding resin on the semiconductor chip. The pulling force due to contraction of the molding resin that leads to warping is proportional to the thickness of the molding resin.