Abstract: A video signal processing device includes: an extraction unit which extracts, from each frame of an input video including a right-eye image and a left-eye image, one of the right-eye image and the left-eye image as an extracted image; and an image enlargement processing unit which (i) forms an interpolated image by enlarging the extracted image extracted by the extraction unit, through pixel interpolation using a pixel included in a previous frame, and (ii) outputs the interpolated image, the previous frame being a frame previous to the frame including the extracted image.

Abstract: An image processor includes a 3D image output section for outputting a 3D image; an average parallax calculator for calculating a parallax level of each predetermined pixel based on a lefty-eye image and a right-eye image, and calculating an average screen parallax level based on the parallax level; a data acquisition section for detecting the type of 3D image or a characteristic of synthesized image; a correcting and synthesizing section for correcting the average screen parallax level depending on the type of 3D image or the characteristic of synthesized image, setting a corrected average parallax level as parallax to be added to the caption or OSD, adding the parallax to the caption or OSD, and synthesizing a caption or OSD with parallax; and an image synthesizer for superimposing the caption or OSD synthesized image with parallax on the 3D image.

Abstract: A power-down determination circuit calculates the horizontal frequency and vertical frequency, respectively, employing a clock signal obtained from a multiplier circuit and horizontal synchronization signal and vertical synchronization signal obtained from a TMDS decode circuit. The power-down determination circuit then determines whether an input digital signal does or does not have a decodable video format by comparing the calculated horizontal frequency and vertical frequency with horizontal frequencies and vertical frequencies stored beforehand, for output of a power-down control signal indicative of the determination. Thus, in the case where the input digital signal does not have a decodable format, the power-down control signal controls a video/audio processing circuit to enter a power-down mode.

Abstract: A power-down determination circuit calculates the horizontal frequency and vertical frequency, respectively, employing a clock signal obtained from a multiplier circuit and horizontal synchronization signal and vertical synchronization signal obtained from a TMDS decode circuit. The power-down determination circuit then determines whether an input digital signal does or does not have a decodable video format by comparing the calculated horizontal frequency and vertical frequency with horizontal frequencies and vertical frequencies stored beforehand, for output of a power-down control signal indicative of the determination. Thus, in the case where the input digital signal does not have a decodable format, the power-down control signal controls a video/audio processing circuit to enter a power-down mode.

Abstract: An interpolation apparatus that generates interpolation pixel values necessary for converting input video data of interlace scanning into video data of progressive scanning is provided. A plurality of candidate pixel-pairs each of which is composed of two pixels that are symmetric with respected to a pixel that is going to be interpolated are selected from pixels on adjacent two scan lines within one field of the input video data, and a difference between pixel values of each selected pixel-pair is calculated. A pixel-pair to be used for generating the interpolation pixel value is determined, based on the smallest difference and the second smallest difference of the calculated differences. An interpolation pixel value of the pixel that is going to be interpolated is generated based on pixel values of the determined pixel-pair.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: A controller and a control method of an integrated memory provided in a system LSI used in television receiver or other video appliance are disclosed. In the memory controller of the invention, when a clock signal suspend command signal not synchronized with a synchronization signal is entered, a suspend command signal synchronized with the synchronization signal is generated. The clock signal supplied in the integrated memory is suspended according to a synchronized suspend command signal. Since the clock signal supply is suspended only while the integrated memory is in idling state, the power consumption of the system LSI can be saved without breaking down the integrated memory.

Abstract: An interpolation apparatus that generates interpolation pixel values necessary for converting input video data of interlace scanning into video data of progressive scanning is provided. A plurality of candidate pixel-pairs each of which is composed of two pixels that are symmetric with respected to a pixel that is going to be interpolated are selected from pixels on adjacent two scan lines within one field of the input video data, and a difference between pixel values of each selected pixel-pair is calculated. A pixel-pair to be used for generating the interpolation pixel value is determined, based on the smallest difference and the second smallest difference of the calculated differences. An interpolation pixel value of the pixel that is going to be interpolated is generated based on pixel values of the determined pixel-pair.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: A television receiver comprising an information extracting circuit for extracting information from a format or content of an input video signal, a video signal processing circuit for processing this video signal by a program or data, a memory for storing the program and data, a CPU for controlling, operating or driving these elements, and a display device for displaying an image. The video signal processing circuit can, under the control of the CPU, decode the signal, correct or set the picture quality such as gradation and sharpness, or adaptively process an on-screen display based on the input video signal. The television receiver is also able to adaptively extend the functions of the television receiver corresponding to various signal formats.