Patents by Inventor Chikara Tsuchiya

Chikara Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8416015
    Abstract: A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 9, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Chikara Tsuchiya
  • Publication number: 20110181218
    Abstract: A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.
    Type: Application
    Filed: April 1, 2011
    Publication date: July 28, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Chikara TSUCHIYA
  • Patent number: 7928601
    Abstract: A DC-DC converter for controlling the order for providing a semiconductor integrated circuit device with a plurality of power supply voltages. A switch control circuit controls activation and inactivation of a transistor of the switch circuit based on the comparison result of a first voltage and a reference voltage and a notification signal provided to the switch control circuit. The switch control circuit generates a second voltage that is higher than the first voltage when the first voltage is higher than the reference voltage and the notification signal indicates that other semiconductor integrated circuit devices are ready to operate.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hidekiyo Ozawa, Hidenobu Ito, Chikara Tsuchiya
  • Patent number: 7777473
    Abstract: A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: August 17, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Morihito Hasegawa, Chikara Tsuchiya, Hidenobu Ito
  • Publication number: 20090051339
    Abstract: A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.
    Type: Application
    Filed: October 23, 2008
    Publication date: February 26, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Morihito Hasegawa, Chikara Tsuchiya, Hidenobu Ito
  • Patent number: 7456623
    Abstract: A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: November 25, 2008
    Assignee: Fujitsu Limited
    Inventors: Morihito Hasegawa, Chikara Tsuchiya, Hidenobu Ito
  • Patent number: 7358946
    Abstract: A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: April 15, 2008
    Assignee: Fujitsu Limited
    Inventors: Masatoshi Kokubun, Shinya Udo, Chikara Tsuchiya
  • Patent number: 7342436
    Abstract: A reduced-size bipolar supply voltage generator which produces a positive and negative voltages from a unipolar power source. A single inductor is employed for current switching operation, where electric energy supplied from a power source is stored in magnetic form, and the stored magnetic energy is released as electric energy. A first and second diodes are connected to first and second ends of the inductor, respectively. The inductor is grounded at the first end via a first switch, while its second end is connected to the power source via a second switch. A switching controller activates both switches to energize the inductor. It then deactivates the first switch alone, thus directing the inductor's energy to the positive voltage output through the first diode. The controller may turn off the second switch alone after energizing the inductor. The stored energy now appears at the negative voltage output through the second diode.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: March 11, 2008
    Assignee: Fujitsu Limited
    Inventors: Chikara Tsuchiya, Kimitoshi Niratsuka, Eiji Nishimori, Katsuyoshi Otsu
  • Publication number: 20070216381
    Abstract: A linear regulator circuit for suppressing power supply noise that propagates to an output voltage. An LDO circuit functioning as the linear regulator circuit is provided with an output transistor including a source for receiving input voltage, a drain for outputting the output voltage, and a control terminal. An error amplifier powered by the input voltage generates a control voltage for controlling the output transistor based on a potential difference between a feedback voltage, which corresponds to the output voltage, and a reference voltage. A first capacitor and a resistor are connected in series between the source of the output transistor and an output terminal of the error amplifier.
    Type: Application
    Filed: August 7, 2006
    Publication date: September 20, 2007
    Inventors: Chikara Tsuchiya, Eiji Nishimori
  • Patent number: 7242427
    Abstract: The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiode 10, a source follower amplifier 14 for converting an electric charge of the photodiode 10 into a voltage and amplifying it to output image data, and a horizontal selection transistor 16 for outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuit 6 has a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: July 10, 2007
    Assignee: Fujitsu Limited
    Inventors: Masatoshi Kokubun, Katsuyosi Yamamoto, Shinya Udo, Jun Funakoshi, Chikara Tsuchiya
  • Publication number: 20070145961
    Abstract: A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.
    Type: Application
    Filed: May 19, 2006
    Publication date: June 28, 2007
    Inventors: Morihito Hasegawa, Chikara Tsuchiya, Hidenobu Ito
  • Patent number: 7224390
    Abstract: A CMOS image sensor that reduces kTC noise in a wide band. A pixel circuit corresponding to one pixel includes a photoelectric conversion element for carrying out the photoelectric conversion of incident light, a reset transistor for resetting a cathode of the photoelectric conversion element to initial voltage, an amplifying transistor for converting electric charges accumulated in the photoelectric conversion element to voltage, and a row selection transistor for selecting signals output from pixel areas arranged in a row direction. A voltage control circuit controls the potential of a gate of the reset transistor during a period when the photoelectric conversion element is reset to change ON-state resistance of the reset transistor. By doing so, a cutoff frequency for a low-pass filter formed in the pixel circuit by ON-state resistance of the reset transistor and parasitic capacitance produced at the cathode on the photoelectric conversion element will be controlled.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: May 29, 2007
    Assignee: Fujitsu Limited
    Inventors: Masatoshi Kokubun, Chikara Tsuchiya
  • Patent number: 7221131
    Abstract: A DC-DC converter for generating power supply voltage differing from input voltage, while operating a semiconductor circuit at a predetermined speed regardless of differences between devices or changes in the operation environment. An output voltage control circuit compares an oscillation signal, which is provided from a ring oscillator of the semiconductor circuit, with a triangular wave signal, which is provided from an oscillator of the DC-DC converter, and changes the output voltage of the DC-DC converter in accordance with the comparison result. This substantially equalizes the oscillation signal of the ring oscillator with the triangular wave signal, which functions as a reference signal, and operates the semiconductor circuit at a speed that is in accordance with the triangular wave signal.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: May 22, 2007
    Assignee: Fujitsu Limited
    Inventors: Hidekiyo Ozawa, Hidenobu Ito, Chikara Tsuchiya, Yasushige Ogawa
  • Patent number: 7196726
    Abstract: The CMOS sensor circuit comprises a photodiode, a reset transistor resetting the photodiode to an initial voltage, and a voltage control circuit controlling a gate potential of the reset transistor to a potential other than power source potentials. The voltage control circuit consists of an inverter circuit driving a gate of the reset transistor. The inverter circuit includes a P-channel MOS transistor, an N-channel MOS transistor, and a transistor inserted between a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor so as to control a blooming.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: March 27, 2007
    Assignee: Fujitsu Limited
    Inventors: Masatoshi Kokubun, Katsuyosi Yamamoto, Chikara Tsuchiya
  • Publication number: 20060139828
    Abstract: A DC-DC converter for controlling the order for providing a semiconductor integrated circuit device with a plurality of power supply voltages. A switch control circuit controls activation and inactivation of a transistor of the switch circuit based on the comparison result of a first voltage and a reference voltage and a notification signal provided to the switch control circuit. The switch control circuit generates a second voltage that is higher than the first voltage when the first voltage is higher than the reference voltage and the notification signal indicates that other semiconductor integrated circuit devices are ready to operate.
    Type: Application
    Filed: April 8, 2005
    Publication date: June 29, 2006
    Inventors: Hidekiyo Ozawa, Hidenobu Ito, Chikara Tsuchiya
  • Publication number: 20060139820
    Abstract: A DC-DC converter for generating power supply voltage differing from input voltage, while operating a semiconductor circuit at a predetermined speed regardless of differences between devices or changes in the operation environment. An output voltage control circuit compares an oscillation signal, which is provided from a ring oscillator of the semiconductor circuit, with a triangular wave signal, which is provided from an oscillator of the DC-DC converter, and changes the output voltage of the DC-DC converter in accordance with the comparison result. This substantially equalizes the oscillation signal of the ring oscillator with the triangular wave signal, which functions as a reference signal, and operates the semiconductor circuit at a speed that is in accordance with the triangular wave signal.
    Type: Application
    Filed: April 8, 2005
    Publication date: June 29, 2006
    Inventors: Hidekiyo Ozawa, Hidenobu Ito, Chikara Tsuchiya, Yasushige Ogawa
  • Patent number: 7019501
    Abstract: A DC/DC converter enabling an increase in frequency. The DC/DC converter includes a main transistor, a synchronization transistor, a control circuit, which controls the main transistor and the synchronization transistor, and a capacitor, which is charged to generate gate voltage for the main transistor. The control circuit includes a charging time setting circuit for setting the activation time of the main transistor and the synchronization transistor.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: March 28, 2006
    Assignee: Fujitsu Limited
    Inventors: Hirofumi Dogome, Takashi Matsumoto, Kyuichi Takimoto, Hidekiyo Ozawa, Chikara Tsuchiya
  • Publication number: 20050270264
    Abstract: A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
    Type: Application
    Filed: July 15, 2005
    Publication date: December 8, 2005
    Inventors: Masatoshi Kokubun, Shinya Udo, Chikara Tsuchiya
  • Patent number: 6946905
    Abstract: A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: September 20, 2005
    Assignee: Fujitsu Limited
    Inventors: Masatoshi Kokubun, Shinya Udo, Chikara Tsuchiya
  • Patent number: 6914631
    Abstract: The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device which has a small element size and a wide opening ratio, and can reduce a kTC noise. A photodiode 10, a reset transistor 12, a source follower amplifier 14, and a horizontal selection transistor 16 are formed in each of pixel regions Pmn. A kTC noise reduction circuit 6VR1 for reducing a kTC noise and a CDS circuit 6CL1 are formed outside of the pixel regions Pmn. A differential amplifier is constituted by a first differential transistor 62 of the kTC noise reduction circuit 6VR1 and the source follower amplifier 14 in each of the pixel regions Pmn.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Shinya Udo, Masatoshi Kokubun, Chikara Tsuchiya, Katsuyosi Yamamoto