Abstract: A line accommodation circuit for use in combination with a cell exchange apparatus to convert a sequence of input data signals into a sequence of asynchronous transfer mode cells is provided with two function systems which are identical in structure. The systems receive the input data signals in parallel and are switched from an active system to a standby system by a switching operation indicated by a system controller. Switching is affected by inserting a test cell in the active system after a last one of the asynchronous transfer mode cell held in the active system, and placed in the standby system before a following asynchronous transfer mode cell. The test cell is first detected by the standby system and thereafter by the active system, at which time the next asynchronous transfer mode cells are sent from the standby system which is rendered into a new active system.

Abstract: In a data exchange for use in an asynchronous transfer mode communication system, the data exchange has first and second buffers. An input data block is selectively loaded with the first and the second buffers to be read as first and second output data blocks out of the first and the second buffers. When the first buffer is changed from an active buffer to a stand-by buffer, the input data block is successively loaded with the first and the second buffers to be memorized as first and second buffered data blocks up to a predetermined block number. A test data block is loaded as the input data block with the first and the second buffers. When the second output data block is coincident with the test data block, the second buffer is controlled so that the second output data block is not read out of the second buffer until the first data block is coincident with the test data block.

Abstract: In a data exchange for use in an asynchronous transfer mode communication system, the data exchange has first and second buffers. An input data block is selectively loaded with the first and the second buffers to be read as first and second output data blocks out of the first and the second buffers. When the first buffer is used as an active buffer, the input data block is loaded with only the first buffer. When the first buffer is changed into a stand-by buffer, the input data block is loaded with the first and the second buffers. A test data block is loaded as the input data block with the first and the second buffers.