Patents by Inventor Chikayuki Kumagai

Chikayuki Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8304662
    Abstract: A buildup board includes a buildup layer having a multilayer structure and/or a core layer having a multilayer structure. The multilayer structure includes a signal wiring pattern, a pad connected to the signal wiring pattern, an insulating part arranged around the pad on the same layer as the pad, and a conductor arranged around the insulating part on the same layer as the pad. The multilayer structure has at least two different keepouts where the keepout is defined as a minimum interval between an outline of the pad and the conductor closest to the pad on the same layer.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: November 6, 2012
    Assignee: Fujitsu Limited
    Inventors: Akiyoshi Saitou, Takeshi Midorikawa, Toru Kuraishi, Chikayuki Kumagai, Masashi Fujimoto, Kenichiro Abe
  • Publication number: 20070295533
    Abstract: A buildup board includes a buildup layer having a multilayer structure and/or a core layer having a multilayer structure. The multilayer structure includes a signal wiring pattern, a pad connected to the signal wiring pattern, an insulating part arranged around the pad on the same layer as the pad, and a conductor arranged around the insulating part on the same layer as the pad. The multilayer structure has at least two different keepouts where the keepout is defined as a minimum interval between an outline of the pad and the conductor closest to the pad on the same layer.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 27, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Akiyoshi Saitou, Takeshi Midorikawa, Toru Kuraishi, Chikayuki Kumagai, Masashi Fujimoto, Kenichiro Abe
  • Publication number: 20070144773
    Abstract: The present invention relates to a circuit board in which signal lines transmitting a signal are wired, and which is capable of increasing the speed of signal transmission. There is provided a circuit board in which signal lines are wired, including: a signal pad which is formed at the tip of the signal line and has a signal via in the center thereof; and plural ground vias which are formed in positions to surround the signal pad and transmit a ground potential over plural wiring layers.
    Type: Application
    Filed: March 27, 2006
    Publication date: June 28, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Akiyoshi Saitou, Toru Kuraishi, Takeshi Midorikawa, Chikayuki Kumagai, Masashi Fujimoto
  • Patent number: 5166867
    Abstract: A massive bus bar for supplying a determined power voltage to a circuit component mounted on a rigid circuit board having a conductor layer connecting the component to a bus bar connecting pad formed on the surface of the board. Plurality of first notches extend through a main surface of the bus bar from a common longitudinal edge, perpendicularly to the longitudinal axis of the bus bar and throughout the full longitudinal extent of the bus bar, and define a plurality of posts which are secured at their bottom surfaces to the conductive pads on the circuit board surface. The first notches facilitate flexing of the bus bar and reduce stresses otherwise produced due to the rigid connection of the bus bar to the circuit board, while not significantly diminishing the current handling capability of the bus bar.
    Type: Grant
    Filed: March 17, 1987
    Date of Patent: November 24, 1992
    Assignee: Fujitsu Limited
    Inventors: Kiyotaka Seyama, Seiichi Saito, Chikayuki Kumagai, Toshinari Hayashi