Patents by Inventor Chikuang Charles Wang

Chikuang Charles Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9881787
    Abstract: Methods for depositing titanium oxide films by atomic layer deposition are disclosed. Titanium oxide films may include a titanium nitride cap, an oxygen rich titanium nitride cap or a mixed oxide nitride layer. Also described are methods for self-aligned double patterning including titanium oxide spacer films.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 30, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Teh Kao, Benjamin Schmiege, Xuesong Lu, Juno Yu-Ting Huang, Yu Lei, Yung-Hsin Lee, Srinivas Gandikota, Rajkumar Jakkaraju, Chikuang Charles Wang, Ghazal Saheli, Benjamin C. Wang, Xinliang Lu, Pingyan Lei
  • Publication number: 20160372324
    Abstract: Methods for depositing titanium oxide films by atomic layer deposition are disclosed. Titanium oxide films may include a titanium nitride cap, an oxygen rich titanium nitride cap or a mixed oxide nitride layer. Also described are methods for self-aligned double patterning including titanium oxide spacer films.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 22, 2016
    Inventors: Chien-Teh Kao, Benjamin Schmiege, Xuesong Lu, Juno Yu-Ting Huang, Yu Lei, Yung-Hsin Lee, Srinivas Gandikota, Rajkumar Jakkaraju, Chikuang Charles Wang, Ghazal Saheli, Benjamin C. Wang, Xinliang Lu, Pingyan Lei
  • Patent number: 7963153
    Abstract: A method, a system and a computer readable medium for dynamic mode AFM amplitude versus distance curve acquisition. In an embodiment, a constant force feedback mechanism is enabled prior to the first time an AFM probe tip contacts a sample. The feedback mechanism setpoint is iteratively reduced while at least phase and amplitude of the probe tip are recorded as a function of the relative z-height of a cantilever coupled to the probe tip. The feedback mechanism setpoint may be repeatedly swept between upper and lower bounds to average out drift between the cantilever and sample. Upon detecting a threshold, an absolute tip-to-sample distance is determined and correlated to the relative z-heights. The amplitude and phase data recorded prior to tip-sample contact is then determined as a function of absolute tip-to-sample distance.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: June 21, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Chikuang Charles Wang, Biao Liu, Yuri S. Uritsky
  • Patent number: 7601648
    Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: October 13, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Thai Cheng Chua, Shankar Muthukrisnan, Johanes Swenberg, Shreyas Kher, Chikuang Charles Wang, Giuseppina Conti, Yuri Uritsky
  • Publication number: 20090139315
    Abstract: A method, a system and a computer readable medium for dynamic mode AFM amplitude versus distance curve acquisition. In an embodiment, a constant force feedback mechanism is enabled prior to the first time an AFM probe tip contacts a sample. The feedback mechanism setpoint is iteratively reduced while at least phase and amplitude of the probe tip are recorded as a function of the relative z-height of a cantilever coupled to the probe tip. The feedback mechanism setpoint may be repeatedly swept between upper and lower bounds to average out drift between the cantilever and sample. Upon detecting a threshold, an absolute tip-to-sample distance is determined and correlated to the relative z-heights. The amplitude and phase data recorded prior to tip-sample contact is then determined as a function of absolute tip-to-sample distance.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 4, 2009
    Inventors: Chikuang Charles Wang, Biao Liu, Yuri S. Uritsky
  • Publication number: 20080026553
    Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Thai Cheng Chua, Shankar Muthukrisnan, Johanes Swenberg, Shreyas Kher, Chikuang Charles Wang, Giuseppina Conti, Yuri Uritsky
  • Publication number: 20080014759
    Abstract: Methods for forming a gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a silicon substrate, depositing a silicon nitride layer on the silicon oxide layer by a thermal process, wherein the silicon oxide layer and the silicon nitride layer are utilized as a gate dielectric layer in a gate structure, and thermally annealing the substrate. In another embodiment, the method includes forming a silicon oxide layer on the silicon substrate with a thickness less than 15 ?, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer with a thickness less than 15 ? by a thermal process, wherein the silicon oxide layer and the silicon nitride layer are utilized as a gate dielectric layer in a gate structure, plasma treating the silicon nitride layer; and thermally annealing the substrate.
    Type: Application
    Filed: July 12, 2006
    Publication date: January 17, 2008
    Inventors: Thai Cheng Chua, Philip Allan Kraus, Christopher Sean Olsen, Cory Czarnik, Chikuang Charles Wang