Abstract: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: A semiconductor device card, such as a memory card for example, includes a semiconductor device, a working voltage indicator, and a working voltage generator. A working voltage indicator is set to indicate a desired level of a working voltage corresponding to the semiconductor device. A working voltage generator generates the working voltage having the desired level and being coupled to the semiconductor device. Thus, the semiconductor device card is easily adaptable to accommodate various working voltages of the semiconductor device.

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: A memory card comprises a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract: A memory card including a non-volatile memory and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory, wherein when the external supply voltage is lower than a detection voltage, the power management unit boosts the external supply voltage and outputs the boosted voltage as the operating voltage of the non-volatile memory.

Abstract: A memory card comprises a non-volatile memory and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory, wherein when the external supply voltage is lower than a detection voltage, the power management unit boosts the external supply voltage and outputs the boosted voltage as the operating voltage of the non-volatile memory.

Abstract: A semiconductor device card, such as a memory card for example, includes a semiconductor device, a working voltage indicator, and a working voltage generator. A working voltage indicator is set to indicate a desired level of a working voltage corresponding to the semiconductor device. A working voltage generator generates the working voltage having the desired level and being coupled to the semiconductor device. Thus, the semiconductor device card is easily adaptable to accommodate various working voltages of the semiconductor device.

Abstract: An integrated circuit memory device includes programmed memory cells and programmable and erasable memory cells. The memory device includes a first memory array block in which programmed memory cells are arranged and a second memory array block in which programmable and erasable memory cells are arranged. The programmed memory cells in the first memory array block may be programmed with predetermined data during a semiconductor manufacturing process, and may be mask read-only memory (ROM) cells. The programmable and erasable memory cells in the second memory array block may be programmed or erased with predetermined data after the semiconductor manufacturing process, and may be electrically erasable and programmable read-only memory (EEPROM) cells or flash memory cells.

Abstract: EEPROM devices may be fabricated by forming a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer on an integrated circuit substrate, and a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and beneath a portion of the gate insulating layer. A first conductive layer, an interlevel insulating layer and a second conductive layer are sequentially formed on the tunnel insulating layer and on the gate insulating layer.

Abstract: EEPROM devices include a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer, on an integrated circuit substrate, and a sense transistor gate on the tunnel insulating layer and on the gate insulating layer. The sense transistor gate includes a floating gate on the tunnel insulating layer and on the gate insulating layer, a first interlevel insulating layer on the floating gate opposite the tunnel insulating layer and the gate insulating layer, and a sense gate on the first interlevel insulating layer opposite the floating gate. A select transistor gate also is included on the gate insulating layer and spaced apart from the sense transistor gate.

Abstract: EEPROM devices may be fabricated by forming a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer on an integrated circuit substrate, and a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and beneath a portion of the gate insulating layer. A first conductive layer, an interlevel insulating layer and a second conductive layer are sequentially formed on the tunnel insulating layer and on the gate insulating layer.

Abstract: EEPROM devices include a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer, on an integrated circuit substrate, and a sense transistor gate on the tunnel insulating layer and on the gate insulating layer. The sense transistor gate includes a floating gate on the tunnel insulating layer and on the gate insulating layer, a first interlevel insulating layer on the floating gate opposite the tunnel insulating layer and the gate insulating layer, and a sense gate on the first interlevel insulating layer opposite the floating gate. A select transistor gate also is included on the gate insulating layer and spaced apart from the sense transistor gate.

Abstract: A semiconductor device is provided having an open drain input/output terminal. The device is formed on a semiconductor substrate of a first conductivity type, having active regions defined by a field oxide layer. A gate insulating layer is formed over the active regions such that it is thicker in an open drain I/O formation area than in a logic formation area. A gate electrode is formed over a predetermined portion of the gate insulating layer, and a second conductivity type junction region for a source/drain is formed in the substrate on both sides of the gate electrode. A field insulating doping layer is formed under the field oxide layer such that it overlaps the junction region in the logic formation part, and is spaced apart from the junction region in the open drain I/O formation part. A second conductivity type impurity region is formed as a channel region under the gate electrode of an enhancement transistor formation part in the open drain I/O formation area.