Abstract: There is provided a method of modifying a first clock to generate a second clock with reduced electromagnetic interference (EMI). The method comprises receiving the first clock, generating an upslew modulation form during an upslew frequency transition, generating a downslew modulation form during a downslew frequency transition, modulating a frequency of the first clock over a period of time using the upslew modulation form and the downslew modulation form to generate the second clock, and wherein the upslew modulation form and the downslew modulation form are different. The upslew modulation form and the downslew modulation form are defined by upslew modulation values and downslew modulation values, respectively, and the method further comprises receiving the upslew modulation values and the downslew modulation values, and generating fractional upslew modulation values and fractional downslew modulation, respectively, for modulating the frequency of the first clock.

Abstract: A single clamp circuit for integrated circuits with multiple V.sub.dd power pins by coupling the various V.sub.dd busses to an ESD clamped V.sub.dd bus or pseudo- V.sub.dd bus via diodes. The diodes will provide coupling from any V.sub.dd bus to the clamp circuit during a positive ESD transient. A diode for each V.sub.dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V.sub.dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses.