Patents by Inventor Chiloda Ashan Senarath PATHIRANE
Chiloda Ashan Senarath PATHIRANE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11429393Abstract: An apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to instructions which reference architectural registers using physical registers to store data values when performing the data processing operations. Mappings between the architectural registers and the physical registers are stored, and when a data hazard condition is identified with respect to out-of-order program execution of an instruction, an architectural register specified in the instruction is remapped to an available physical register. A reorder buffer stores an entry for each destination architectural register specified by the instruction, entries being stored in program order, and an entry specifies a destination architectural register and an original physical register to which the destination architectural register was mapped before the architectural register remapped to an available physical register.Type: GrantFiled: November 11, 2015Date of Patent: August 30, 2022Assignee: ARM LIMITEDInventors: Vladimir Vasekin, Ian Michael Caulfield, Chiloda Ashan Senarath Pathirane
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Patent number: 11416252Abstract: A data processing system includes an instruction pipeline containing instruction queue circuitry, fusion circuitry and decoder circuitry. The fusion circuitry serves to identify fusible groups of program instructions within a Y-wide window of program instructions and supply a stream of program instructions including such replacement fused program instructions to a X-wide decoder circuitry which decodes X program instructions in parallel using parallel decoders.Type: GrantFiled: December 27, 2017Date of Patent: August 16, 2022Assignee: Arm LimitedInventors: Vladimir Vasekin, Chiloda Ashan Senarath Pathirane, Jungsoo Kim, Alexei Fedorov
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Patent number: 11216277Abstract: Aspects of the present disclosure relate to an apparatus comprising register circuitry implementing a plurality of registers and processing circuitry to perform data processing operations on data stored in said registers. The apparatus comprises store buffer circuitry to, responsive to a store instruction in respect of given data, temporarily store said given data prior to providing said given data to a memory. Responsive to receiving at the processing circuitry a request to perform a state-saving-triggering operation, the register circuitry is configured to capture in shadow registers of said register circuitry a state of a subset of registers of the plurality of registers, provide the captured state from the shadow registers to the memory.Type: GrantFiled: September 26, 2019Date of Patent: January 4, 2022Assignee: Arm LimitedInventor: Chiloda Ashan Senarath Pathirane
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Patent number: 11068238Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.Type: GrantFiled: May 21, 2019Date of Patent: July 20, 2021Assignee: Arm LimitedInventors: Michael Alexander Kennedy, Neil Burgess, Zichao Xie, Chiloda Ashan Senarath Pathirane
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Patent number: 11036510Abstract: A merging predicated instruction controls a processing pipeline to perform a processing operation to determine a processing result based on at least one source operand, and to perform a merging operation to merge the processing result with a previous value of a destination register under control of a predicate value identifying, for each of a plurality of portions of the destination register, whether that portion is to be set to a corresponding portion of the processing result or a corresponding portion of the previous value. The merging predicated instruction is permitted to be issued to the pipeline with a timing which results in the previous value of the destination register still being unavailable when the merging predicated instruction is at a given pipeline stage at which the processing result is determined. This can help to improve performance of subsequent instructions which are independent of the merging predicated instruction.Type: GrantFiled: October 11, 2018Date of Patent: June 15, 2021Assignee: Arm LimitedInventors: Karel Hubertus Gerardus Walters, Chiloda Ashan Senarath Pathirane
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Publication number: 20210096863Abstract: Aspects of the present disclosure relate to an apparatus comprising register circuitry implementing a plurality of registers and processing circuitry to perform data processing operations on data stored in said registers. The apparatus comprises store buffer circuitry to, responsive to a store instruction in respect of given data, temporarily store said given data prior to providing said given data to a memory. Responsive to receiving at the processing circuitry a request to perform a state-saving-triggering operation, the register circuitry is configured to capture in shadow registers of said register circuitry a state of a subset of registers of the plurality of registers, provide the captured state from the shadow registers to the memory.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Inventor: Chiloda Ashan Senarath PATHIRANE
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Patent number: 10963253Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.Type: GrantFiled: July 10, 2018Date of Patent: March 30, 2021Assignee: Arm LimitedInventors: Karel Hubertus Gerardus Walters, Chiloda Ashan Senarath Pathirane, Michael Alexander Kennedy
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Publication number: 20200371749Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Inventors: Michael Alexander KENNEDY, Neil BURGESS, Zichao XIE, Chiloda Ashan Senarath PATHIRANE
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Patent number: 10719329Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry.Type: GrantFiled: June 28, 2018Date of Patent: July 21, 2020Assignee: Arm LimitedInventors: Vladimir Vasekin, David Michael Bull, Chiloda Ashan Senarath Pathirane, Alexei Fedorov
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Publication number: 20200117457Abstract: A merging predicated instruction controls a processing pipeline to perform a processing operation to determine a processing result based on at least one source operand, and to perform a merging operation to merge the processing result with a previous value of a destination register under control of a predicate value identifying, for each of a plurality of portions of the destination register, whether that portion is to be set to a corresponding portion of the processing result or a corresponding portion of the previous value. The merging predicated instruction is permitted to be issued to the pipeline with a timing which results in the previous value of the destination register still being unavailable when the merging predicated instruction is at a given pipeline stage at which the processing result is determined. This can help to improve performance of subsequent instructions which are independent of the merging predicated instruction.Type: ApplicationFiled: October 11, 2018Publication date: April 16, 2020Inventors: Karel Hubertus Gerardus WALTERS, Chiloda Ashan Senarath PATHIRANE
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Patent number: 10552160Abstract: A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.Type: GrantFiled: May 23, 2018Date of Patent: February 4, 2020Assignee: ARM LimitedInventors: Ian Michael Caulfield, Max John Batley, Chiloda Ashan Senarath Pathirane
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Publication number: 20200019402Abstract: An apparatus comprises instruction decoding circuitry to generate micro-operations in response to program instructions; and processing circuitry to perform data processing in response to the micro-operations generated by the instruction decoding circuitry. In response to a predicated vector instruction, the instruction decoding circuitry reads or predicts an estimated value of the predicate value, and depending on the estimated value, varies a composition of at least one micro-operation generated in response to the predicated vector instruction. This can enable more efficient use of hardware resources in the processing circuitry.Type: ApplicationFiled: July 10, 2018Publication date: January 16, 2020Inventors: Karel Hubertus Gerardus WALTERS, Chiloda Ashan Senarath PATHIRANE, Michael Alexander KENNEDY
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Publication number: 20200004547Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Vladimir VASEKIN, David Michael BULL, Chiloda Ashan Senarath PATHIRANE, Alexei FEDOROV
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Publication number: 20190196832Abstract: A data processing system 2 includes an instruction pipeline 14 containing instruction queue circuitry 28, fusion circuitry 30 and decoder circuitry 32. The fusion circuitry 30 serves to identify fusible groups of program instructions within a Y-wide window of program instructions and supply a stream of program instructions including such replacement fused program instructions to a X-wide decoder circuitry 32 which decodes X program instructions in parallel using parallel decoders 40, 42, 44.Type: ApplicationFiled: December 27, 2017Publication date: June 27, 2019Inventors: Vladimir VASEKIN, Chiloda Ashan Senarath PATHIRANE, Jungsoo KIM, Alexei FEDOROV
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Patent number: 10296349Abstract: Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to indicate the register index of the allocated source and destination processor registers; the avocation circuitry being selectively operable to allocate, to a processor instruction, a group of destination processor registers having a subset of their register indices in common and to associate, with the processor instruction, information to indicate the register index of one processor register of the group and identifying information to identify one or more bits of the register index which differ between the processor registers in the allocated group of processor registers.Type: GrantFiled: January 7, 2016Date of Patent: May 21, 2019Assignee: ARM LimitedInventors: Vladimir Vasekin, Antony John Penton, Chiloda Ashan Senarath Pathirane, Andrew James Antony Lees
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Publication number: 20180267805Abstract: A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.Type: ApplicationFiled: May 23, 2018Publication date: September 20, 2018Inventors: Ian Michael CAULFIELD, Max John BATLEY, Chiloda Ashan Senarath PATHIRANE
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Publication number: 20170199738Abstract: Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to indicate the register index of the allocated source and destination processor registers; the avocation circuitry being selectively operable to allocate, to a processor instruction, a group of destination processor registers having a subset of their register indices in common and to associate, with the processor instruction, information to indicate the register index of one processor register of the group and identifying information to identify one or more bits of the register index which differ between the processor registers in the allocated group of processor registers.Type: ApplicationFiled: January 7, 2016Publication date: July 13, 2017Inventors: Vladimir VASEKIN, Antony John PENTON, Chiloda Ashan Senarath PATHIRANE, Andrew James Antony LEES
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Publication number: 20170139716Abstract: A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.Type: ApplicationFiled: November 18, 2015Publication date: May 18, 2017Inventors: Ian Michael CAULFIELD, Max John BATLEY, Chiloda Ashan Senarath PATHIRANE
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Publication number: 20170132010Abstract: An apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to instructions which reference architectural registers using physical registers to store data values when performing the data processing operations. Mappings between the architectural registers and the physical registers are stored, and when a data hazard condition is identified with respect to out-of-order program execution of an instruction, an architectural register specified in the instruction is remapped to an available physical register. A reorder buffer stores an entry for each destination architectural register specified by the instruction, entries being stored in program order, and an entry specifies a destination architectural register and an original physical register to which the destination architectural register was mapped before the architectural register remapped to an available physical register.Type: ApplicationFiled: November 11, 2015Publication date: May 11, 2017Inventors: Vladimir VASEKIN, Ian Michael CAULFIELD, Chiloda Ashan Senarath PATHIRANE