Patents by Inventor Chi-Lun Lo

Chi-Lun Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240413830
    Abstract: A successive-approximation register analog-to-digital converter (SAR ADC) with comparator error detection is shown, which introduces a comparator error detector to detect errors of the comparators used in the SAR ADC. Digital control bits controlling a digital-to-analog converter (DAC) of the SAR ADC include most significant bits (MSBs) and least significant bits (LSBs), and the DAC is configured to provide redundancy approximation at the lowest bit of the MSBs. The comparators include a plurality of MSB comparators corresponding to the MSBs. The comparator error detector detects the occurrence of a comparator error based on the LSBs, and identifies the target comparator that is causing the comparator error based on the MSBs.
    Type: Application
    Filed: June 11, 2024
    Publication date: December 12, 2024
    Inventors: Tsung-Kai KAO, Chi-Lun LO
  • Patent number: 9628035
    Abstract: An implementation of an operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: April 18, 2017
    Assignee: MEDIATEK INC.
    Inventors: Hung-Chieh Tsai, Chi-Lun Lo, Chen-Yen Ho, Yu-Hsin Lin
  • Patent number: 9584146
    Abstract: Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 28, 2017
    Assignee: MediaTek Inc.
    Inventors: Frank Op 't Eynde, Nathan Egan, Khurram Muhammad, Tien-Yu Lo, Chi-Lun Lo, Michael A. Ashburn
  • Publication number: 20170033801
    Abstract: A delta-sigma modulator includes a signal subtraction circuit, a loop filter, a quantizer, a digital-to-analog converter (DAC), and a control circuit. The signal subtraction circuit subtracts an analog feedback signal from an analog input signal to generate a difference signal. The loop filter performs a filtering operation upon the difference signal to generate a filtered signal. The quantizer quantizes the filtered signal into a digital out put signal, wherein at least one inherent circuit characteristic of the quantizer are adjusted in response to a digital code input. The DAC generates the analog feedback signal according to the digital output signal. The control circuit generates the digital code input to the quantizer for setting an excess loop delay (ELD) compensation.
    Type: Application
    Filed: January 20, 2015
    Publication date: February 2, 2017
    Applicant: Mediatek Singapore PTE. LTD.
    Inventors: Chi-Lun Lo, Stacy Ho
  • Patent number: 9461660
    Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency response modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency response compensator coupled to the frequency response modifier, wherein the frequency response compensator compensates for the modification introduced by the frequency response modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency response compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 4, 2016
    Assignee: MEDIATEK INC.
    Inventors: Khurram Muhammad, Chi-Lun Lo, Frank Op 't Eynde, Michael A. Ashburn, Jr., Tien-Yu Lo
  • Publication number: 20160211856
    Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency compensator coupled to the frequency modifier, wherein the frequency compensator compensates for the modification introduced by the frequency modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.
    Type: Application
    Filed: November 11, 2015
    Publication date: July 21, 2016
    Inventors: Khurram MUHAMMAD, Chi-Lun LO, Frank OP 'T EYNDE, Michael A. ASHBURN, JR., Tien-Yu LO
  • Publication number: 20160211861
    Abstract: Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.
    Type: Application
    Filed: October 19, 2015
    Publication date: July 21, 2016
    Applicant: MediaTek Inc.
    Inventors: Frank Op 't Eynde, Nathan Egan, Khurram Muhammad, Tien-Yu Lo, Chi-Lun Lo, Michael A. Ashburn
  • Publication number: 20160204793
    Abstract: Systems and methods for reducing spurious noise tones in sigma-delta analog-to-digital converters (ADCs) are described. A dither signal may be added to two differential input signals of a pseudo-differential sigma-delta ADC. The dither signal may be generated by a pseudo-random bit sequence generator and applied to two input buffers, which add the dither signal to received differential analog input signals. The dithered signals may be digitized by two independent sigma-delta ADCs and then subtracted to remove the dither signal from an overall digital output signal.
    Type: Application
    Filed: September 1, 2015
    Publication date: July 14, 2016
    Applicant: MediaTek Inc.
    Inventors: Frank Op 't Eynde, Chi-Lun Lo, Michael A. Ashburn
  • Patent number: 9385745
    Abstract: Systems and methods for reducing spurious noise tones in sigma-delta analog-to-digital converters (ADCs) are described. A dither signal may be added to two differential input signals of a pseudo-differential sigma-delta ADC. The dither signal may be generated by a pseudo-random bit sequence generator and applied to two input buffers, which add the dither signal to received differential analog input signals. The dithered signals may be digitized by two independent sigma-delta ADCs and then subtracted to remove the dither signal from an overall digital output signal.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 5, 2016
    Assignee: MediaTek Inc.
    Inventors: Frank Op 't Eynde, Chi-Lun Lo, Michael A. Ashburn
  • Patent number: 9154083
    Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level. The AC-coupled push-pull output stage further includes a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier. Further, the AC-coupled push-pull output stage includes an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 6, 2015
    Assignee: MEDIATEK INC.
    Inventors: Chen-Yen Ho, Chi-Lun Lo, Hung-Chieh Tsai, Yu-Hsin Lin
  • Publication number: 20150180420
    Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level. The AC-coupled push-pull output stage further includes a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier. Further, the AC-coupled push-pull output stage includes an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor.
    Type: Application
    Filed: March 10, 2015
    Publication date: June 25, 2015
    Inventors: Chen-Yen HO, Chi-Lun LO, Hung-Chieh TSAI, Yu-Hsin LIN
  • Patent number: 9007249
    Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level; a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor; and a resistance component, coupling the gate of the first transistor to a bias voltage level.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 14, 2015
    Assignee: MediaTek Inc.
    Inventors: Chen-Yen Ho, Chi-Lun Lo, Hung-Chieh Tsai, Yu-Hsin Lin
  • Publication number: 20150028951
    Abstract: An implementation of an operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Hung-Chieh TSAI, Chi-Lun LO, Chen-Yen HO, Yu-Hsin LIN
  • Patent number: 8890611
    Abstract: An operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 18, 2014
    Assignee: MediaTek Inc.
    Inventors: Hung-Chieh Tsai, Chi-Lun Lo, Chen-Yen Ho, Yu-Hsin Lin
  • Patent number: 8891707
    Abstract: A receiving device includes: a mixer module arranged to receive an input signal to generate a down-converted output; a first active filter, the first active filter arranged to receive the down-converted output and perform an active filtering process upon the down-converted output to generate a first filtered output; a passive filter, the passive filter arranged to receive the first filtered output and perform a passive filtering process upon the first filtered output to generate a second filtered output; and a processing circuit, the processing circuit arranged to receive the second filtered output and process the second filtered output to generate an output signal corresponding to the input signal.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 18, 2014
    Assignee: MediaTek Inc.
    Inventors: Chi-Lun Lo, Chia-Hsin Wu, Tsung-Ling Li
  • Patent number: 8810308
    Abstract: A filter is provided. The filter receives an input signal and generates an output signal according to the input signal. The filter includes an input network, a high-pass network, and an operational circuit. The first input network provides a first normal path for the input signal to generate a first normal signal. The first high-pass network provides a first high-pass path for the input signal to generate a first high-pass signal. The operational circuit has first and second input terminals. The polarity of the second input terminal is inverse to that of the first input terminal. The operational circuit receives the first normal signal by the first input terminal and the first high-pass signal by the second input terminal such that a subtraction operation is performed on the first normal signal and the first high-pass filter to accomplish a low-pass filtering operation for generating the output signal.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: August 19, 2014
    Assignee: MediaTek Inc.
    Inventors: Yu-Hsin Lin, Hung-Chieh Tsai, Chi-Lun Lo, Chen-Yen Ho
  • Patent number: 8791848
    Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator includes a multi-stage loop filter, a quantizer, and a digital-to-analog converter. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. Each stage of the multi-stage loop filter includes a feedback network. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. The digital-to-analog converter receives the digital output signal and converts the digital output signal to a compensation signal. The digital-to-analog converter provides the compensation signal to a plurality of internal nodes in the feedback network of the last stage of the multi-stage loop filter.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: July 29, 2014
    Assignee: Mediatek Inc.
    Inventors: Chen-Yen Ho, Chi-Lun Lo, Hung-Chieh Tsai, Yu-Hsin Lin
  • Publication number: 20140103999
    Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level; a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor; and a resistance component, coupling the gate of the first transistor to a bias voltage level.
    Type: Application
    Filed: December 19, 2013
    Publication date: April 17, 2014
    Applicant: MediaTek Inc.
    Inventors: Chen-Yen HO, Chi-Lun LO, Hung-Chieh TSAI, Yu-Hsin LIN
  • Patent number: 8638250
    Abstract: An amplifier, a fully-differential amplifier and a delta-sigma modulator are disclosed. The disclosed amplifier includes a front-end gain stage, an AC-coupled push-pull output stage and a compensation circuit. The compensation circuit is coupled between the front-end gain stage and an output terminal of the amplifier. The AC-coupled push-pull output stage uses an AC-coupled capacitor (which is a passive two terminal electrical component rather than a stray or parasitic capacitance of a transistor) to couple the front-end gain stage to a gate of a top or bottom transistor of a push-pull structure introduced in the AC-coupled push-pull output stage, and uses a resistance component to couple a gate of the top or bottom transistor (depending on which one is coupled to the AC-coupled capacitor) to a bias voltage level.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: January 28, 2014
    Assignee: Mediatek Inc.
    Inventors: Chen-Yen Ho, Chi-Lun Lo, Hung-Chieh Tsai, Yu-Hsin Lin
  • Patent number: 8575970
    Abstract: An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Mediatek Inc.
    Inventors: Hung-Chieh Tsai, Yu-Hsin Lin, Chi-Lun Lo, Jong-Woei Chen