Patents by Inventor Chil Woo Kwon

Chil Woo Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11171107
    Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu Jin Choi, Sung Hoan Kim, Chang Eun Joo, Chil Woo Kwon, Young Kyu Lim, Sung Uk Lee
  • Publication number: 20200335468
    Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.
    Type: Application
    Filed: December 13, 2019
    Publication date: October 22, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu Jin Choi, Sung Hoan Kim, Chang Eun Joo, Chil Woo Kwon, Young Kyu Lim, Sung Uk Lee
  • Publication number: 20160374198
    Abstract: A printed circuit board includes a core layer including a glass core, a first resin layer disposed on a first surface of the glass core, and a second resin layer formed on a second surface of the glass core; build-up layers disposed on the first and second surfaces of the core layer; and a conductive pattern formed in multiple layers on the build-up layers, wherein the core layer has asymmetric coefficients of thermal expansion opposing sides thereof with respect to a center of the glass core in a thickness direction.
    Type: Application
    Filed: January 21, 2016
    Publication date: December 22, 2016
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Heung-Kyu KIM, Suk-Hyeon CHO, Chil-Woo KWON, Yul-Kyo CHUNG, Going-Sik KIM
  • Publication number: 20150223341
    Abstract: An embedded board, a printed circuit board, and a method of manufacturing the same. According to one embodiment of the present invention, an embedded board includes: a core insulating layer formed with a first cavity; a first circuit layer formed on one surface of the core insulating layer; a build-up insulating layer formed on one surface of the core insulating layer and formed with a second cavity extending from the first cavity; devices disposed in the first cavity and the second cavity and formed to protrude from one surface of the core insulating layer; a first insulating layer formed on the other surface of the core insulating layer and filling the first cavity and the second cavity; and a build-up circuit layer and a via formed in the build-up insulating layer.
    Type: Application
    Filed: January 15, 2015
    Publication date: August 6, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Hoon KIM, Tae Hong MIN, Young Gwan KO, Hye Jin KIM, Suk Hyeon CHO, Chil Woo KWON, Jung Han LEE
  • Publication number: 20110089138
    Abstract: Disclosed is a method of manufacturing a printed circuit board, including (A) forming a first circuit layer on a base substrate and forming a first insulating layer thereon, (B) forming trenches including dummy trenches and wiring trenches on the first insulating layer and plating the trenches, thus providing a trench circuit layer including a dummy circuit pattern and a wiring circuit pattern, (C) removing the dummy circuit pattern of the trench circuit layer, and (D) forming a second insulating layer on the trench circuit layer from which the dummy circuit pattern was removed. The method reduces deviation of plating thickness and thus realizes the design density of a trench circuit layer.
    Type: Application
    Filed: December 9, 2009
    Publication date: April 21, 2011
    Inventors: Young Gwan Ko, Ryoichi Watanabe, Sang Soo Lee, Hee Bum Shin, Se Won Park, Chil Woo Kwon