Patents by Inventor Chi-Nan Chen
Chi-Nan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921001Abstract: A method and system for inspecting deviation in dynamic characteristics of a feeding system are provided, and the method includes: exciting the feeding system and detecting vibrations of a subcomponent of a component to be inspected of the feeding system to generate a monitoring excitation signal in a monitoring mode; calculating, by a modal analysis method, monitoring eigenvalues and monitoring eigenvectors of the monitoring excitation signal; determining, by a modal verification method, similarity between the monitoring eigenvalues and standard eigenvalues of a digital twin model and similarity between the monitoring eigenvectors and standard eigenvectors of the digital twin model; determining that the dynamic characteristics of the subcomponent are deviated, when the monitoring eigenvalues and monitoring eigenvectors are not similar to the standard eigenvalues and standard eigenvectors. Therefore, the subcomponent whose dynamic characteristics are deviated can be sensed remotely and precisely.Type: GrantFiled: March 11, 2022Date of Patent: March 5, 2024Assignee: Hiwin Technologies Corp.Inventors: Hsien-Yu Chen, Yu-Sheng Chiu, Chih-Chun Cheng, Wen-Nan Cheng, Chi-Ming Liu
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Publication number: 20240071535Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.Type: ApplicationFiled: October 16, 2022Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Chung-Hao Chen, Chi-Hsiu Hsu, Chi-Fa Lien, Ying-Ting Lin, Cheng-Hsiao Lai, Ya-Nan Mou
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Publication number: 20220317582Abstract: A wafer edge exposure method includes: providing a wafer, the edge of the wafer having multiple regions to be exposed and non-exposed regions adjacent to the plurality of regions to be exposed; and providing a wafer edge exposure device, aligning in sequence the wafer edge exposure device with each of the regions to be exposed while isolating from the non-exposed regions, and exposing each of the regions to be exposed. The wafer edge exposure method, the wafer edge exposure device, and the mask can reduce the damage to effective wafers during the exposure process while ensuring the exposure effect of the wafers.Type: ApplicationFiled: March 23, 2021Publication date: October 6, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: CHI-NAN CHEN
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Publication number: 20180053776Abstract: A memory device is provided. The memory device includes a substrate and a first stack structure. The first stack structure includes a tunneling layer. The tunneling layer includes SixOyNz, wherein x:y is 1:0.1 to 1:10, and x:z is 1:0.1 to 1:10. The first stack structure further includes a charge layer disposed over the tunneling layer and a first silicon oxide layer disposed over the charge layer. The first stack structure further includes a first gate line disposed over the first silicon oxide layer. The memory device further includes a source line doped region disposed in the substrate and disposed at the first side of the first stack structure. The memory device further includes a bit line doped region disposed in the substrate and disposed at the second side of the first stack structure. A method for manufacturing the memory device is also provided.Type: ApplicationFiled: August 16, 2016Publication date: February 22, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Chi-Nan CHEN, Jen-Chuan PAN
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Patent number: 5629521Abstract: An infrared detector device is described. It is based on an infrared analog of the Fabry Perot interferometer, using one curved, fully reflecting, plate and one planar, mainly reflecting, but partially transmitting, plate. The space between these plates behaves as a resonant cavity which can be built to respond to either a broad or a narrow band of wavelengths in the general range between 1 and 15 microns. It is also possible to combine several detectors of different narrow bands in a single device. Actual detection of the radiation is based on use of thin film resistors, having a high thermal coefficient of resistance, that are thermally isolated from the other parts of the structure. Details relating to the manufacture of the devices are given.Type: GrantFiled: September 9, 1996Date of Patent: May 13, 1997Assignee: Industrial Technology Research InstituteInventors: Shih-ping Lee, Chi-Nan Chen
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Patent number: 5584117Abstract: An infrared detector device is described. It is based on an infrared analog of the Fabry Perot interferometer, using one curved, fully reflecting, plate and one planar, mainly reflecting, but partially transmitting, plate. The space between these plates behaves as a resonant cavity which can be built to respond to either a broad or a narrow band of wavelengths in the general range between 1 and 15 microns. It is also possible to combine several detectors of different narrow bands in a single device. Actual detection of the radiation is based on use of thin film resistors, having a high thermal coefficient of resistance, that are thermally isolated from the other parts of the structure. Details relating to the manufacture of the devices are given.Type: GrantFiled: December 11, 1995Date of Patent: December 17, 1996Assignee: Industrial Technology Research InstituteInventors: Shih-ping Lee, Chi-Nan Chen
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Patent number: 5580387Abstract: A corrugated waveguide is disclosed comprising a cylindrical body with outer and inner surfaces. The inner surface is provided with plurality of ridges uniformly spaced around the inner surface. Presence of 2n ridges secures the formation of microwaves with stable TE.sub.n1 modes where n is an integer and n>1. Disclosed also is an electron cyclotron resonance system for plasma processing of which system the corrugated waveguide described in the above is a part.Type: GrantFiled: June 28, 1995Date of Patent: December 3, 1996Assignee: Electronics Research & Service OrganizationInventor: Chi-Nan Chen
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Patent number: 5446426Abstract: A microwave power combiner is formed in a cylindrical hollow metallic housing utilizing a number of pie shaped chambers formed with metallic vanes attached to and extending radially inward from the interior sidewalls of the cylindrical hollow metallic housing. Individual microwave power sources exterior to the cylindrical hollow metallic housing transmit energy into the pie shaped chambers. Two ring shaped metallic vane straps are used to control impedance mismatches and the resonant frequency of the microwave power combiner. The microwave power from the individual microwave power sources combine in the cylindrical hollow metallic housing and is extracted through the circular top of the cylindrical hollow metallic housing by means of a waveguide or a transmission line. The individual microwave power sources can be replaced as needed without affecting impedance matching or the efficiency of power transfer. There is flexibility in the number of individual microwave power sources used.Type: GrantFiled: December 27, 1994Date of Patent: August 29, 1995Assignee: Industrial Technology Research InstituteInventors: Jen-chau Wu, Chi-Nan Chen
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Patent number: D627592Type: GrantFiled: February 2, 2010Date of Patent: November 23, 2010Assignee: Highlight Tech System CorporationInventors: Bie-Joe Wen, Chi-Nan Chen, Ming-Jyh Hwang, Feng-Tsung Cheng