Patents by Inventor Chin C. Wang

Chin C. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6833625
    Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, the interconnect opening is filled with a conductive fill material comprised of a bulk conductive fill material doped with a first dopant element and a second dopant element that is different from the first dopant element. The dielectric material is comprised of a first dielectric reactant element and a second dielectric reactant element. A diffusion barrier material is formed from a reaction of the first dielectric reactant element and the first dopant element that diffuses from the conductive fill material to the walls to the interconnect opening. In addition, a boundary material is formed from a reaction of the second dielectric reactant element and the second dopant element that diffused from the conductive fill material to the walls of the interconnect opening.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: December 21, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Fei Wang
  • Patent number: 6831003
    Abstract: For filling an interconnect opening within a porous dielectric material, a diffusion barrier material is deposited onto at least one sidewall of the interconnect opening. A thickness of the diffusion barrier material is equal to or greater than a radius of a pore opened at the sidewall to substantially fill the opened pore. The thickness of the diffusion barrier material is equal to or greater than a mean radius of pores opened at the sidewall to substantially fill a majority of the opened pores. Or, the thickness of the diffusion barrier material is equal to or greater than a radius of a largest pore opened at the sidewall to substantially fill all opened pores. The interconnect opening is then filled with a conductive fill material.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: December 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Huang, Pin-Chin C. Wang, Darrell M. Erb
  • Patent number: 6664185
    Abstract: For fabricating an interconnect structure within a dielectric material comprised of at least one dielectric reactant element, an interconnect opening formed within the dielectric material is filled with a conductive fill material comprised of first and second dopant elements that are different. A diffusion barrier material, that surrounds the conductive fill material, is formed from a reaction of the first dopant element and a dielectric reactant element. Also, a boundary material, that surrounds the conductive fill material, is formed from a reaction of the second dopant element and a dielectric reactant element. The boundary material prevents diffusion of a dielectric reactant element from the dielectric material into the conductive fill material.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: December 16, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Fei Wang
  • Publication number: 20030217462
    Abstract: The reliability and electromigration performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor substrate, are enhanced by a method for more reliably and uniformly diffusing into a conductive fill alloying elements which reduce or substantially prevent electromigration. The method comprises depositing around a conductive fill metal alloy films and alloying layers comprising one or more alloying elements having physical and/or chemical attributes which are effective for minimizing or substantially preventing electromigration along grain boundaries and/or along the interface between the surfaces of the conductive fill and other surfaces. The metal alloy films and alloying layers are advantageously deposited where their particular physical and/or chemical attributes may be most beneficial for improving electromigration performance.
    Type: Application
    Filed: December 13, 2001
    Publication date: November 27, 2003
    Inventors: Fei Wang, Brian J. MacDonald, Amit P. Marathe, John E. Sanchez, Pin-Chin C. Wang, Joffre F. Bernard
  • Patent number: 6573179
    Abstract: A strong interface is formed between an interconnect and an encapsulating layer to prevent the lateral drift of material from the interconnect along the bottom of the encapsulating layer. Diffusion barrier material is deposited on the top surface of the interconnect using a selective deposition process. The diffusion barrier material may be epitaxially grown from the interconnect during the selective deposition of the diffusion barrier material on the top surface of the interconnect to promote adhesion of the diffusion barrier material to the interconnect. An encapsulating layer is deposited on top of the diffusion barrier material. The diffusion barrier material and the encapsulating layer are comprised of a similar chemical element to promote adhesion of the diffusion barrier material to the encapsulating layer. The diffusion barrier material on the top surface of the interconnect prevents lateral drift of material comprising the interconnect along the encapsulating layer.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: June 3, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Lu You
  • Patent number: 6528412
    Abstract: For filling an interconnect opening within an insulating layer on a semiconductor wafer, an adhesion skin layer is deposited conformally onto an underlying material comprised of one of a barrier material or a dielectric material at sidewalls and a bottom wall of the interconnect opening. The adhesion skin layer includes a metal alloy doping element. A conformal seed layer is deposited onto the adhesion skin layer using a conformal deposition process, such as an ECD (electrochemical deposition) or a CVD (chemical-vapor-deposition) process. The adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material at the sidewalls and the bottom wall of the interconnect opening. The interconnect opening is filled with a conductive material grown from the conformal seed layer. In this manner, the adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material to minimize electromigration failure of the interconnect.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: March 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Sergey Lopatin
  • Patent number: 6447933
    Abstract: An alloy material is formed on an underlying material, and the alloy material comprises an alloy doping element mixed into a bulk material. A first layer of material including the alloy doping element is deposited on the underlying material using a first type of deposition process. The first type of deposition process is corrosion resistive to the underlying material according to one aspect of the present invention. A second layer of material including the bulk material is deposited on the first layer of material using a second type of deposition process. A thermal anneal may be performed by heating the first layer of material and the second layer of material such that the alloy doping element is mixed into the bulk material to form the alloy material on the underlying material. The alloy doping element of the first layer of material deposited on the underlying material promotes adhesion of the alloy material to the underlying material.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Sergey Lopatin
  • Patent number: 6426293
    Abstract: A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of each of the test interconnect structures has a respective thickness and a respective concentration of an alloy dopant within a bulk conductive material. A respective thermal anneal process is performed at a respective thermal anneal temperature for each of the plurality of test interconnect structures. A respective resistance and a respective rate of electromigration failure is measured for each of the plurality of test interconnect structures. For forming an IC interconnect structure within an IC interconnect opening, an alloy seed layer is deposited onto sidewalls and a bottom wall of the IC interconnect opening, and the IC interconnect opening is filled by growing a fill conductive material from the alloy seed layer within the IC interconnect opening.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: July 30, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Sergey Lopatin, Amit P. Marathe
  • Patent number: 6387806
    Abstract: An interconnect opening of an integrated circuit is filled with a conductive fill, such as copper, with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first alloy is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The first alloy is comprised of a first metal dopant in a bulk conductive material. The first metal dopant has a relatively high solid solubility in the bulk conductive material, and the first metal dopant has a concentration in the bulk conductive material of the seed layer that is lower than the solid solubility of the first metal dopant in the bulk conductive material.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: May 14, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Christy M. Woo
  • Patent number: 6358840
    Abstract: In a method for filling an interconnect opening to form an interconnect of an integrated circuit, the interconnect opening is formed within an insulating layer. The interconnect opening is partially filled with a conductive material to form a recess within the conductive material toward a top of the interconnect opening, and the recess is disposed within the interconnect opening. An alloy is conformally deposited to fill the recess. Any conductive material and the alloy on the insulating layer are polished away such that the conductive material and the alloy are contained within the interconnect opening. A thermal anneal is then performed such that the conductive material and the alloy form into a conductive fill of a single grain structure within the interconnect opening. An additional encapsulating material is formed to cover a top surface of the conductive fill during the thermal anneal from the dopant of the alloy diffusing out of the alloy and along the top surface of the conductive fill.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: March 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Christy M. Woo
  • Patent number: 6309959
    Abstract: An interconnect opening of an integrated circuit is filled with a conductive fill with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first conductive material is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The interconnect opening is further filled with a second conductive material by growing the second conductive material from the seed layer to form a conductive fill of the first conductive material and the second conductive material within the interconnect opening. The first conductive material and the second conductive material are comprised of a bulk metal, and at least one of the first conductive material and the second conductive material is a metal alloy having an alloy dopant in the bulk metal. In addition, a plasma treatment process is performed to remove any metal oxide or metal hydroxide from a top surface of the conductive fill.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 30, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Lu You, Joffre Bernard, Amit Marathe
  • Patent number: 6228759
    Abstract: An alloy precipitate is formed to surround a conductive fill within an interconnect opening, including especially a top surface of the conductive fill, to prevent drift of material from the conductive fill into the insulating layer that is surrounding the interconnect opening. An alloy material is deposited non-conformally such that the alloy material is deposited substantially only toward a top of the sidewalls of an interconnect opening and substantially only toward a center of the bottom wall of the interconnect opening. The interconnect opening is filled with the conductive material by growing the conductive material from a seed layer of the conductive material to form a conductive fill of the conductive material within the interconnect opening. The semiconductor wafer is heated to anneal the conductive fill within the interconnect opening such that the conductive fill forms into a substantially single grain structure.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: May 8, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Christy M. Woo, Sergey Lopatin
  • Patent number: 6207552
    Abstract: A strong interface is fabricated by forming and filling a recess on top of an interconnect between the interconnect and an encapsulating layer to prevent the lateral drift of material from the interconnect along the bottom of the encapsulating layer. A recess is formed within the top surface of the interconnect, and diffusion barrier material is deposited within the recess on the top surface of the interconnect. The diffusion barrier material may be epitaxially grown from the interconnect during the deposition of the diffusion barrier material within the recess to promote adhesion of the diffusion barrier material to the interconnect. An encapsulating layer is deposited on top of the diffusion barrier material. The diffusion barrier material and the encapsulating layer are comprised of a similar chemical element to promote adhesion of the diffusion barrier material to the encapsulating layer.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: March 27, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Lu You
  • Patent number: 4947873
    Abstract: A microcomputer-controlled fully automatic lighting unit has a transmission line including a motor and necessary driving mechanism which, when being started, is able to deliver cigarettes to a place where they will be lighted by an induced electric heatable wire. The unit further has another transmission line including a motor and necessary driving mechanism which may send the lighted cigarette out of the unit and thereby safely and automatically completes a cycle of cigarette lighting procedure.
    Type: Grant
    Filed: July 31, 1989
    Date of Patent: August 14, 1990
    Inventor: Chin C. Wang
  • Patent number: 4517117
    Abstract: An improved conductive molding composition for the preparation of high density capacitance electronic discs is disclosed. The disclosed compositions are improved by the replacement of most or all of the conventionally used stabilizer ingredient with a tin mercapto ester or alkyl mercaptide represented by the formulae ##STR1## wherein R is a straight-chain alkyl radical having 4 to 8 carbon atoms; R.sub.1 is selected from --S-CH.sub.2 -COOR.sub.3 and --S-R.sub.3 ;R.sub.2 is R or R.sub.1 ; andR.sub.3 is a straight-chain alkyl radical having from 8 to 18 carbon atoms.
    Type: Grant
    Filed: June 20, 1984
    Date of Patent: May 14, 1985
    Assignee: RCA Corporation
    Inventors: Mohamed E. Labib, Chin C. Wang