Patents by Inventor Chin-Chang Cheng

Chin-Chang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7964174
    Abstract: An apparatus and method for forming catalyst particles to grow nanotubes is disclosed. In addition, an apparatus and method for forming nanotubes using the catalytic particles is also disclosed. The particles formed may have different diameters depending upon how they are formed. Once formed, the particles are deposited on a substrate. Once deposited, the mobility of the particles is restricted and nanotubes and/or nanotube portions are grown on the particles. Nanotube portions having different diameters may be formed and the portions may be connected to form nanotubes with different diameters along the length of the nanotube.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: June 21, 2011
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Juan E. Dominguez, Chin-Chang Cheng
  • Publication number: 20100164108
    Abstract: A method for forming a copper interconnect is described. An opening in a dielectric layer disposed on a substrate is formed. A barrier layer is formed on the opening. A seed layer is formed on the barrier layer. The seed layer includes a noble metal copper alloy, the copper having less than 50% of the atomic weight of the noble metal copper alloy.
    Type: Application
    Filed: March 11, 2010
    Publication date: July 1, 2010
    Inventors: Steven W. Johnston, Chin-Chang Cheng
  • Patent number: 7694413
    Abstract: A method for forming a copper interconnect is described. An opening in a dielectric layer disposed on a substrate is formed. A barrier layer is formed on the opening. A seed layer is formed on the barrier layer. The seed layer includes a noble metal copper alloy, the copper having less than 50% of the atomic weight of the noble metal copper alloy.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Chin-Chang Cheng
  • Patent number: 7663230
    Abstract: A method of forming channels on a die or other substrate. Also disclosed are liquid cooling systems including such channels.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Chin Chang Cheng, Alan M. Myers
  • Patent number: 7629252
    Abstract: Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, bonding the coupling agent to the dielectric material within the opening, and electrolessly depositing the barrier material layer, wherein the electrolessly deposited barrier material layer material adheres to the catalytic metal of the coupling agent.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Chin-Chang Cheng, Ramanan V. Chebiam, Valery M. Dubin, Sridhar Balakrishnan
  • Patent number: 7597763
    Abstract: Electroless plating systems and methods are described herein.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: October 6, 2009
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Arnel Fajardo, Chin-Chang Cheng
  • Publication number: 20090078794
    Abstract: A nozzle assembly is connected to a pipe and includes an insertion port in which a resilient filtering member is inserted. Teeth are defined in an inner periphery of the insertion port and a diameter of the resilient filtering member is slightly larger than an inner diameter of the insertion port. The teeth press inward an outer surface of the resilient filtering member so as to position the filtering member in the insertion port.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Inventor: Chin-Chang Cheng
  • Patent number: 7470617
    Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Ramanan Chebiam, Chin-Chang Cheng, Damian Whitney, Harsono Simka
  • Publication number: 20080311400
    Abstract: An apparatus and method for forming catalyst particles to grow nanotubes is disclosed. In addition, an apparatus and method for forming nanotubes using the catalytic particles is also disclosed. The particles formed may have different diameters depending upon how they are formed. Once formed, the particles are deposited on a substrate. Once deposited, the mobility of the particles is restricted and nanotubes and/or nanotube portions are grown on the particles. Nanotube portions having different diameters may be formed and the portions may be connected to form nanotubes with different diameters along the length of the nanotube.
    Type: Application
    Filed: August 25, 2008
    Publication date: December 18, 2008
    Inventors: Valery M. Dubin, Juan E. Dominguez, Chin-Chang Cheng
  • Publication number: 20080213994
    Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 4, 2008
    Inventors: Ramanan Chebiam, Chin-Chang Cheng, Damian Whitney, Harsono Simka
  • Publication number: 20080185714
    Abstract: A method of forming channels on a die or other substrate. Also disclosed are liquid cooling systems including such channels.
    Type: Application
    Filed: April 4, 2008
    Publication date: August 7, 2008
    Inventors: Shriram Ramanathan, Chin Chang Cheng, Alan M. Myers
  • Publication number: 20080087742
    Abstract: A surface cooling device includes a cover fixed to a surface and a pipe is engaged with a groove an underside of the cover. A plurality of nozzles are rotatably connected to the pipe and located in outlets defined through the cover. The nozzles spray water particles to the air to cool the surface such as a road.
    Type: Application
    Filed: September 25, 2007
    Publication date: April 17, 2008
    Inventor: Chin-Chang Cheng
  • Patent number: 7358201
    Abstract: A method of forming channels on a die or other substrate. Also disclosed are liquid cooling systems including such channels.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: April 15, 2008
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Chin Chang Cheng, Alan M. Myers
  • Publication number: 20080000678
    Abstract: A method for forming a copper interconnect is described. An opening in a dielectric layer disposed on a substrate is formed. A barrier layer is formed on the opening. A seed layer is formed on the barrier layer. The seed layer includes a noble metal copper alloy, the copper having less than 50% of the atomic weight of the noble metal copper alloy.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Steven W. Johnston, Chin-Chang Cheng
  • Patent number: 7285494
    Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventors: Chin-Chang Cheng, Valery M. Dubin
  • Patent number: 7262504
    Abstract: A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactive reducing agents, and second, forming a bulk metal layer over the thin metal layer by using an electroless plating solution containing mildly reactive reducing agents. Through this two stage method, the use of highly reactive reducing agents that may cause the formation of contaminant particles may be minimized. By minimizing the formation of contaminant particles in the electroless plating solution, the lifetime of the solution may be extended and the current leakage between metal interconnect lines may be reduced.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Chin-Chang Cheng, Valery M. Dubin
  • Publication number: 20070148952
    Abstract: Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, bonding the coupling agent to the dielectric material within the opening, and electrolessly depositing the barrier material layer, wherein the electrolessly deposited barrier material layer material adheres to the catalytic metal of the coupling agent.
    Type: Application
    Filed: December 23, 2005
    Publication date: June 28, 2007
    Inventors: Kevin O'Brien, Chin-Chang Cheng, Ramanan Chebiam, Valery Dubin, Sridhar Balakrishnan
  • Patent number: 7223694
    Abstract: A method of depositing a metal cladding on conductors in a damascene process is described. The potential between, for instance, cobalt ions in electroless solution and the surface of an ILD between the conductors is adjusted so as to repel the metal from the ILD.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Chin-Chang Cheng, Valery M. Dubin, Peter K. Moon
  • Publication number: 20070066081
    Abstract: A method of forming a metal interconnect for an integrated circuit comprises providing a substrate that includes a trench formed in a dielectric layer, employing a first dry thermal process to deposit a barrier layer onto the dielectric layer and within the trench, employing a second dry thermal process to deposit a catalytic activation film on the barrier layer, employing a wet chemistry plating process to deposit at least one metal layer on the catalytic activation film to fill the trench, and planarizing the deposited metal layer to form an interconnect. The first and second dry thermal processes may be vapor deposition processes performed in sequence within a reaction chamber under vacuum, where the vacuum is not broken between processes. The wet chemistry plating process may be an electroless plating process or a combination of an electroless plating process and an electroplating process.
    Type: Application
    Filed: September 21, 2005
    Publication date: March 22, 2007
    Inventors: Chin-Chang Cheng, Yang Cao
  • Publication number: 20060216929
    Abstract: An etch stopless interconnect structure. According to embodiments of the present invention, a via opening is formed in an interlayer dielectric over a metal layer to expose a portion of the metal layer. The opening is then partially filled with a gap fill material. The opening is then filled with a sacrificial material wherein the sacrificial material is formed on the gap fill material. A trench is then formed in the interlayer dielectric including a portion of the opening filled with the sacrificial material. The sacrificial material is then removed from the opening. The trench and opening are then filled with a conductive film.
    Type: Application
    Filed: March 28, 2005
    Publication date: September 28, 2006
    Inventors: Hyun-Mog Park, Chin-Chang Cheng