Abstract: A conductive bump electrode structure includes a substrate, an elastic circuit layer, at least two conductive bumps, and an insulating layer. The elastic circuit layer is mounted on the substrate, and includes at least one elastic circuit. The at least two conductive bumps are mounted on the elastic circuit layer, and are electrically connected to each other through the at least one elastic circuit. The insulating layer is mounted on the elastic circuit layer, and includes at least two holes. Since there is a gap between the conductive bumps, the conductive bump electrode structure is easy to be bent and fit body curves of various parts of a user. The elastic circuit can stretch or compress along with the user's movement due to its elasticity, thereby increasing suitability of the conductive bump electrode structure to the human body.

Abstract: A conductive bump electrode structure includes a substrate, an elastic circuit layer, at least two conductive bumps, and an insulating layer. The elastic circuit layer is mounted on the substrate, and includes at least one elastic circuit. The at least two conductive bumps are mounted on the elastic circuit layer, and are electrically connected to each other through the at least one elastic circuit. The insulating layer is mounted on the elastic circuit layer, and includes at least two holes. Since there is a gap between the conductive bumps, the conductive bump electrode structure is easy to be bent and fit body curves of various parts of a user. The elastic circuit can stretch or compress along with the user's movement due to its elasticity, thereby increasing suitability of the conductive bump electrode structure to the human body.

Abstract: The present invention provides a system and a method for measuring physiological signal. The system includes a plurality of electrodes and a measurement apparatus. A plurality of first electrodes of the electrodes are attached on a first area of a subject. A plurality of second electrodes of the electrodes are attached on a second area of the subject. The measurement apparatus is coupled to the electrodes and performs testing on the first electrodes and the second electrodes to obtain a plurality of testing results. The measurement apparatus selects one of the first electrodes as a first measuring electrode and selects one of the second electrodes as a second measuring electrode according to the testing results. The measurement apparatus measures a physiological signal of the subject through the first measuring electrode and the second measuring electrode.

Abstract: A physiological signal receiving apparatus and a manufacturing method thereof are provided. The physiological signal receiving apparatus includes an electrode layer, a protective layer and a conductive structure electrically connected to the electrode layer. The electrode layer is disposed on a substrate. The electrode layer includes a porous gel and a plurality of conductive particles distributed therein. The protective layer is disposed on the substrate and the electrode layer. The protective layer has an opening exposing a portion of the electrode layer. The porous gel is expanded after absorbing liquid, such that a surface of the electrode layer exposed by the opening is higher than a surface of the protective layer.

Abstract: The present invention provides a system and a method for measuring physiological signal. The system includes a plurality of electrodes and a measurement apparatus. A plurality of first electrodes of the electrodes are attached on a first area of a subject. A plurality of second electrodes of the electrodes are attached on a second area of the subject. The measurement apparatus is coupled to the electrodes and performs testing on the first electrodes and the second electrodes to obtain a plurality of testing results. The measurement apparatus selects one of the first electrodes as a first measuring electrode and selects one of the second electrodes as a second measuring electrode according to the testing results. The measurement apparatus measures a physiological signal of the subject through the first measuring electrode and the second measuring electrode.

Abstract: A physiological signal receiving apparatus and a manufacturing method thereof are provided. The physiological signal receiving apparatus includes an electrode layer, a protective layer and a conductive structure electrically connected to the electrode layer. The electrode layer is disposed on a substrate. The electrode layer includes a porous gel and a plurality of conductive particles distributed therein. The protective layer is disposed on the substrate and the electrode layer. The protective layer has an opening exposing a portion of the electrode layer. The porous gel is expanded after absorbing liquid, such that a surface of the electrode layer exposed by the opening is higher than a surface of the protective layer.

Abstract: System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the integrated circuit, the top structure including a first metal material, which includes a first electrical terminal and a second electrical terminal. The test structure also includes a bottom structure positioned below the integrated circuit, the bottom structure including a first silicon material. A first side structure is positioned between the top structure and the bottom structure and located next to a first side of the integrated circuit. A second side structure is positioned between the top structure and the bottom structure and located next to a second side of the integrated circuit.

Abstract: A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within an active area in a substrate, and the active area is adjacent to at least an isolation region in the substrate. Additionally, the system includes a polysilicon region. The polysilicon region is separated from the substrate by a dielectric layer, and the polysilicon region intersects each of the plurality of gate regions. At least a part of the polysilicon region is on the active area.

Abstract: An electronic device is provided. The electronic device includes a base, a battery module and an upper cover. The battery module is disposed in the base. The battery module includes a tray and at least one battery unit. The battery unit is disposed on the tray. The upper cover is connected to the base and covers the battery module.

Abstract: System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing a chip. For example, the test structure and the chip are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the chip. For example, the top structure can be characterized by a first surface area. The top structure includes a first metal material occupying less than 60% of the surface area. The test structure also includes a bottom structure positioned below the chip. For example, the bottom structure can be characterized by a second surface area. The second surface area is substantially equal to the first surface area. The bottom structure includes a first silicon material. The first silicon material occupies substantially all of the second surface area.

Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.

Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions. The plurality of polysilicon regions are separated from the first substrate a plurality of dielectric layers.

Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.

Abstract: System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing a chip. For example, the test structure and the chip are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the chip. For example, the top structure can be characterized by a first surface area. The top structure includes a first metal material occupying less than 60% of the surface area. The test structure also includes a bottom structure positioned below the chip. For example, the bottom structure can be characterized by a second surface area. The second surface area is substantially equal to the first surface area. The bottom structure includes a first silicon material. The first silicon material occupies substantially all of the second surface area.

Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions.

Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region.

Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region.