Abstract: A method and device for disabling a communication device of a communication network that includes a second communication device. The communication device includes an electronic processor configured to perform an examination of a behavior of the communication device, determine, based on a result of the examination of a behavior of the communication device, a score of the communication device, and disable, in response to the score exceeding a predetermined threshold, the communication device.

Abstract: Disclosed are techniques that can be used within network devices to implement access control functionality. The techniques can include use of a content-addressable memory configured including an access control entry stored therein. Circuitry can be coupled to the content-addressable memory and configured to determine that a value is within a range of values. The circuitry can generate a compare key including a field that is set indicating that the value is within the range of values. The circuitry can provide, to the content-addressable memory, the compare key for locating a corresponding access control entry within the content-addressable memory. The circuitry can receive, from the content-addressable memory, an index of the access control entry stored within the content-addressable memory. The circuitry can select, based on the index of the access control entry, an action.

Abstract: A method for monitoring the depth of at least one via (11) in a wafer comprising the steps of arranging the via (11) as a capacitive plate (21), providing a corresponding capacitive plate (23), applying an electrical potential difference to the via (11) and the corresponding capacitive plate (23), measuring the resultant capacitance between the via (11) and a corresponding capacitive plate (23) and determining the depth of the at least one via (11) by the capacitance.

Abstract: An on-chip capacitor having a plurality of capacitor layers Each capacitor layer comprising a pair of frames, such that a first frame of the pair is electrically connected to first frames on each other capacitor layer and a second frame of the pair is electrically connected to second frames on each other capacitor layer; A plurality of tines projecting from each frame within the respective capacitor layer, the tines from each frame meshing so as to form an array of sequentially alternating tines from each frame to provide a layer capacitance within the capacitor layer, wherein the multi-layer capacitor further includes a plurality of projections from said tines, said projections extending between frames of adjacent capacitor layers so as to provide an interstitial capacitance between the capacitor layers, wherein the total capacitance of the on-chip capacitor is the sum of each layer capacitance and each interstitial capacitance.