Abstract: A method of fabricating transistors on a semiconductor substrate includes forming transistor gates of first and second transistors located in first and second areas of the semiconductor substrate, respectively. The transistor gates have generally vertical sidewalls. Source and drain regions are simultaneously formed for the first and second transistors. Temporary spacers are formed on the vertical sidewalls of the first and second transistor gates. The temporary spacers of the first transistor abut a semiconductor structure such that the source and drain regions of the first transistor are vertically covered. The temporary spacers of the second transistor cover a portion of the source and drain regions of the second transistor such that a portion of the source and drain regions remain exposed. The semiconductor substrate is exposed to an implant dopant to change the dopant level of the exposed portions of the source and drain regions of the second transistors.

Abstract: A method of fabricating transistors on a semiconductor substrate includes forming transistor gates of first and second transistors located in first and second areas of the semiconductor substrate, respectively. The transistor gates have generally vertical sidewalls. Source and drain regions are simultaneously formed for the first and second transistors. Temporary spacers are formed on the vertical sidewalls of the first and second transistor gates. The temporary spacers of the first transistor abut a semiconductor structure such that the source and drain regions of the first transistor are vertically covered. The temporary spacers of the second transistor cover a portion of the source and drain regions of the second transistor such that a portion of the source and drain regions remain exposed. The semiconductor substrate is exposed to an implant dopant to change the dopant level of the exposed portions of the source and drain regions of the second transistors.

Abstract: A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

Abstract: A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

Abstract: A method and apparatus for producing photoluminescence emissions (68) from thin CaF.sub.2 films grown on either silicon or silicon/aluminum substrate shows narrow emission linewidth and high emission intensities for CaF.sub.2 with thickness as low as 0,2 .mu.m, The preferred embodiment is doped with a rare-earth such as Nd.

Abstract: A semiconductor device and process for making the same with reduced capacitance between adjacent conductors on a connection layer. This technique works best at narrow conductor spacing (less than 1 micron), where the need for lower dielectric constant intralayer insulation materials accelerates. Directional deposition of a dielectric layer 14 at an acute angle relative to the plane of a semiconductor substrate 10 forms bridges between the tops of narrowly spaced conductors 12, resulting in the formation of one or more gas dielectric regions 18. The process is self-aligning, using the shadowing effect of the conductors themselves to mask deposition of dielectric material between them, and only bridges between conductors which are closely spaced. Subsequent deposition of an interlayer dielectric 20 completes a typical structure. The directional deposition method may, for instance, be electron beam evaporation of a material such as SiO.sub.2, Si.sub.3 N.sub.4, polyimide, or amorphous Teflon.