Patents by Inventor Chin-Chen Lin

Chin-Chen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972562
    Abstract: A method for determining a plant growth curve includes obtaining color images and depth images of a plant to be detected at different time points, performing alignment processing on each color image and each depth image to obtain an alignment image, detecting the color image through a pre-trained target detection model to obtain a target bounding box, calculating an area ratio of the target bounding box in the color image, determining a depth value of all pixel points in the target boundary frame according to the aligned image, performing denoising processing on each depth value to obtain a target depth value, generating a first growth curve of the plant to be detected according to the target depth values and corresponding time points, and generating a second growth curve of the plant to be detected according to the area ratios and the corresponding time points.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: April 30, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chih-Te Lu, Chin-Pin Kuo, Tzu-Chen Lin
  • Patent number: 11967582
    Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11967547
    Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11954875
    Abstract: A method for determining a height of a plant, an electronic device, and a storage medium are disclosed. In the method, a target image is obtained by mapping an obtained color image with an obtained depth image. The electronic device processes the color image by using a pre-trained mobilenet-ssd network, obtains a detection box appearance of the plant, and extracts target contours of the plant to be detected from the detection box. The electronic device determines a depth value of each of pixel points in the target contour according to the target image. Target depth values are obtained by performing a de-noising on depth values of the pixel points, and a height of the plant to be detected is determined according to the target depth value. The method improves accuracy of height determination of a plant.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 9, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Tzu-Chen Lin, Chih-Te Lu, Chin-Pin Kuo
  • Publication number: 20240106192
    Abstract: Disclosed herein are electronic devices that include arrays of dual function light transmit and receive pixels. The pixels of such arrays include a photodetector (PD) structure and a vertical-cavity, surface-emitting laser (VCSEL) diode, both formed in a common stack of epitaxial semiconductor layers. The pixels of the array may be configured by a controller or processor to function either as a light emitter by biasing the VCSEL diode, or as a light detector or receiver by a different bias applied to the PD structure, and this functionality may be altered in time. The array of dual function pixels may be positioned interior to an optical display of an electronic device, in some cases to provide depth sensing or autofocus. The array of pixels may be registered with a camera of an electronic device, such as to provide depth sensing or autofocus.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Fei Tan, Keith Lyon, Tong Chen, Chin Han Lin, Xiaofeng Fan, Arnaud Laflaquiere
  • Patent number: 11935894
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Patent number: 7175412
    Abstract: A heat pressing die set for forming embossed designs on garments includes a male and a female die seat on which a silicon and a metal die are respectively supported. The silicon and the metal die are cut according to given designs to form complementary male and female die surfaces. Continuous flat belt zones of a predetermined width are separately provided on the silicon and the metal die corresponding to perimeters of the given designs. When an area of a garment is clamped and heat-pressed between the silicon and metal dies, the given designs are embossed on the garment and surrounded by heat-pressed belts, which visually highlight the embossed designs while protect non-embossed areas on the garment against undesired pull and stretch to therefore upgrade the quality of the embossed designs.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: February 13, 2007
    Inventor: Chin-Chen Lin
  • Publication number: 20040137103
    Abstract: A heat pressing die set for forming embossed designs on garments includes a male and a female die seat on which a silicon and a metal die are respectively supported. The silicon and the metal die are cut according to given designs to form complementary male and female die surfaces. Continuous flat belt zones of a predetermined width are separately provided on the silicon and the metal die corresponding to perimeters of the given designs. When an area of a garment is clamped and heat-pressed between the silicon and metal dies, the given designs are embossed on the garment and surrounded by heat-pressed belts, which visually highlight the embossed designs while protect non-embossed areas on the garment against undesired pull and stretch to therefore upgrade the quality of the embossed designs.
    Type: Application
    Filed: January 15, 2003
    Publication date: July 15, 2004
    Inventor: Chin-Chen Lin