Patents by Inventor Chin Cheng

Chin Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250247029
    Abstract: A sensorless motor control system includes a drive unit and a control unit. The drive unit includes a motor having three phase windings and a rotor, and an actuation circuit connected to the three phase windings. The actuation circuit includes three switch units each including a high-side switch and a low-side switch. The control unit is configured to alternately actuate the high-side switches respectively of the three switch units and the low-side switches respectively of the three switch units such that the high-side switch of one of the three switch units and the low-side switch of a different one of the three switch units are actuated during each of a plurality of detection cycle periods, record an actuation duration during each of the detection cycle periods, and determine a position of the rotor based on the actuation durations recorded respectively for the detection cycle periods.
    Type: Application
    Filed: December 17, 2024
    Publication date: July 31, 2025
    Applicant: BASSO INDUSTRY CORP
    Inventors: Cheng-En TSAI, Pei-Yuan Hung, Chin-Cheng Lee, Hung-Wei Chen
  • Publication number: 20250197409
    Abstract: Provided is a bifunctional compound, or a pharmaceutically acceptable salt, hydrate, solvate, metabolite or prodrug thereof, wherein the bifunctional compound is represented by Formula (I): ABM-L-CLM??(I); wherein: ABM is an androgen receptor binding moiety; -L- is a linking moiety; and CLM is a cereblon E3 ubiquitin ligase binding moiety represented by Formula (II)-1: wherein one end of the -L- is covalently joined to Q3, Q4, Q5 or Q6; and the other end of the -L- is covalently joined to the ABM. Also provided are a pharmaceutical composition comprising the bifunctional compound and a method for treating an androgen receptor related disease or disorder by administering the bifunctional compound.
    Type: Application
    Filed: June 29, 2023
    Publication date: June 19, 2025
    Inventors: Chu-Chiang Lin, Hung-Chuan Chen, Pei-Chin Cheng, Chih-Chang Chou
  • Publication number: 20250170693
    Abstract: An elastomer selecting mechanism for safety sliding bar of a nail gun, comprising defining a falling height of the nail gun and an allowed contraction amount of the elastomer, and determining an ideal elastic coefficient of the elastomer under the condition of the allowed contraction amount based on the gravitational potential energy obtained at the falling height of the nail gun, and then selecting the elastomer based on the ideal elastic coefficient. The elastomer has a maximum elastic coefficient to avoid permanent deformation of the safety sliding bar and a minimum elastic coefficient to maintain the touching and pressing feel of the safety sliding bar. The ideal elastic coefficient is limited by the maximum elastic coefficient and the minimum elastic coefficient to ensure the touching and pressing feel of the safety sliding bar and to avoid permanent deformation when the nail gun is subject to falling impact.
    Type: Application
    Filed: July 18, 2024
    Publication date: May 29, 2025
    Inventors: YING-CHIEH LIU, CHIN-CHENG CHEN, HAI-LUN MA, LU-CHEN STAN CHEN
  • Patent number: 12301656
    Abstract: A method is provided for managing over-the-top delivery of content through a plurality of content delivery networks (CDN). The method provided works transparently with standard HTTP servers supporting an initial request for content from a client to a first preferred CDN. If the first CDN does not have the content, the method includes provisions for the first CDN to acquire the content from a second CDN, or for the client to request the content from a second CDN directly. A system is also specified for implementing a client and server infrastructure in accordance with the provisions of the method.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: May 13, 2025
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Kevin J. Ma, Raj Nair, Robert Hickey, Daniel Biagini, Chin-Cheng Wu
  • Patent number: 12292815
    Abstract: A method for system profiling and controlling and a computer system performing the same are provided. In the method, an operating system is operated after the computer system is booted, in which a profiling-controlling system is operated. When the operating system loads and executes a system profiling-controlling program, the profiling-controlling system that simultaneously operates a profiling routine and a controlling routine is initiated. The profiling routine is used to retrieve system kernel data that is generated during operation of the operating system and analyze the system kernel data through a kernel tracing tool. When it is determined that controlling is required, the profiling routine notifies the controlling routine. The controlling routine controls operating parameters of the operating system in real time according to an analysis result generated by the profiling routine.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: May 6, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Kuan Wu, Sheng-Kai Hung, Tsai-Wei Wu, Tsai-Chin Cheng, Yu-Kuen Wu
  • Publication number: 20250125212
    Abstract: An integrated circuit with a metal thin film includes: a packaging shell with a top surface, a plurality of side surfaces and a bottom surface. The side surfaces each have one end connected to the top surface and the other surface connected to the bottom surface. The bottom surface includes a plurality of metal pins; and a metal thin film layer coated on the top surface, or at least one of the side surfaces, or both the top surface and at least one of the side surfaces.
    Type: Application
    Filed: September 4, 2024
    Publication date: April 17, 2025
    Inventors: Chih-Hsiang Lin, Chin-Cheng Lo
  • Publication number: 20250096147
    Abstract: An overlay mark includes a previous layer mark and a current layer mark. The previous layer mark includes a plurality of first work zones. Each first working zone includes a first sub-region and a second sub-region, wherein the first sub-region is closer to a center point of the previous layer mark than the second sub-region. The previous layer mark includes a first mark and an auxiliary mark respectively in the first sub-region and the second sub-region of each first working zone. The current layer mark includes a plurality of second working zones. Each second working zone includes a first sub-region and a second sub-region. The current layer mark includes a second mark disposed in the second sub-region of each second working zone. The overlay mark may be applied in the process of manufacturing a 3D NAND flash memory with high capacity and high performance.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chiung Jung Tu, Chih-Hao Huang, Yu-Lin Liu, Chin-Cheng Yang
  • Publication number: 20250068467
    Abstract: A contiguous memory allocation device includes a memory and a processor. The memory is configured to store at least one command. The processor is configured to read the at least one command to execute following steps: calculating a page thrashing value of the memory; determining a corresponding relation between the page thrashing value and a predetermined thrashing value; and deciding whether to lend a contiguous memory according to the corresponding relation.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 27, 2025
    Inventors: Yi-Kuan WU, Hsiang-Wei SUNG, Meng-Sin WU, Sheng-Kai HUNG, Tsai-Chin CHENG
  • Patent number: 12235543
    Abstract: An electronic device is provided. The electronic device includes a frame, a working panel, a case, and an adhesive material. The frame includes a side wall and a back plate. The working panel is disposed on the back plate. The case is disposed on the frame and adjacent to the working panel. The adhesive material is disposed on the case. The side wall has an outer surface facing away from the working panel. In a cross-section view of the electronic device, a portion of the adhesive material is in contact with the outer surface of the side wall of the frame, and a length of the adhesive material is greater than or equal to 50% of a length of the side wall of the frame along an extension direction.
    Type: Grant
    Filed: March 19, 2024
    Date of Patent: February 25, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Wen-Cheng Huang, Ting-Sheng Chen, Chia-Chun Yang, Chin-Cheng Kuo
  • Publication number: 20250056781
    Abstract: A layout pattern of static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions and a plurality of gate structures are located on the substrate, each diffusion region includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each gate structure spans the plurality of diffusion regions. The plurality of gate structures include a first gate structure, the first gate structure includes a first L-shaped portion, which spans the first diffusion region and the fifth diffusion region and forms a first pull-down transistor (PD1), the first diffusion region is adjacent to and in direct contact with the fifth diffusion region.
    Type: Application
    Filed: September 13, 2023
    Publication date: February 13, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Lin Chen, Tsung-Hsun Wu, Liang-Wei Chiu, Yao-Chin Cheng
  • Patent number: 12205894
    Abstract: A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: January 21, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Cheng Yang, Yun-Chu Lin
  • Patent number: 12204839
    Abstract: A method is disclosed herein. The method includes: providing, by an electronic design automation (EDA), a trigger signal to an application programming interface (API); providing, by the API, first parameters associated with parameterized cells in a netlist of an integrated circuit (IC); adjusting, by the API, the first parameters to generate second parameters associated with the parameterized cells in the netlist of the IC; updating, by the API, the netlist of the IC according to the second parameters; and performing, by the EDA, a simulation according to the netlist.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsun-Yu Yang, Ren-Hong Fu, Chin-Cheng Kuo, Jui-Feng Kuan
  • Patent number: 12197785
    Abstract: A controller integrated circuit (IC) and a method for controlling a storage device for a host device to enhance overall performance are provided. The host device may include the controller IC, where the storage device is positioned outside the host device. The controller IC may include a plurality of first queues, a first queue notification register and a first queue auxiliary notification register, where each first queue of the first queues is arranged to queue first queue entries for being used to interact with the storage device. The first queue notification register may store first queue notification information for indicating whether any first queue of the plurality of first queues sends any first interrupt. The first queue auxiliary notification register may store first queue auxiliary notification information for indicating which first queue of the plurality of first queues is the any first queue that has sent the any first interrupt.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: January 14, 2025
    Assignee: MEDIATEK INC.
    Inventors: Chin-Chin Cheng, Chih-Chieh Chou, Tzu-Shiun Liu
  • Publication number: 20250015012
    Abstract: A semiconductor integrated circuit, a semiconductor device and a method for aligning semiconductor integrated circuits are provided. The semiconductor integrated circuit includes a substrate and an overlay mark structure in the substrate. The overlay mark structure includes first overlay marks and second overlay marks separated from each other. A first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventor: Chin-Cheng YANG
  • Publication number: 20240427626
    Abstract: A system includes a host, a storage host controller, and a storage device. The host includes a hypervisor for running a first virtual machine and a second virtual machine. The storage host controller includes a plurality of first multi-circular queues (MCQs) assigned to the first virtual machine and a plurality of second MCQs assigned to the second virtual machine. The plurality of first MCQs assigned to the first virtual machine is used to control operations of the first virtual machine. The plurality of second MCQs assigned to the second virtual machine is used to control operations of the second virtual machine. The storage device has a first portion linked to the first virtual machine for being accessed by the first virtual machine, and a second portion linked to the second virtual machine for being accessed by the second virtual machine wherein the first portion and the second portion are isolated.
    Type: Application
    Filed: June 25, 2024
    Publication date: December 26, 2024
    Applicant: MEDIATEK INC.
    Inventors: Liang-Yen Wang, Chih-Chieh Chou, Chin-Chin Cheng
  • Patent number: 12175134
    Abstract: A host system operates to manage a storage device. The host system initiates an abort of a command when the command has been fetched from a submission queue (SQ) of the host system and the SQ entry has been fetched from the SQ and the host system has not received a corresponding command completion response from the storage device. The host system sends an abort request to the storage device, and issues a cleanup request to direct a host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry to indicate completion of the abort request.
    Type: Grant
    Filed: February 22, 2024
    Date of Patent: December 24, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Chin Chin Cheng, Szu-Chi Liu
  • Publication number: 20240394456
    Abstract: A method is disclosed herein. The method includes: providing, by an electronic design automation (EDA), a trigger signal to an application programming interface (API); providing, by the API, first parameters associated with parameterized cells in a netlist of an integrated circuit (IC); adjusting, by the API, the first parameters to generate second parameters associated with the parameterized cells in the netlist of the IC; updating, by the API, the netlist of the IC according to the second parameters; and performing, by the EDA, a simulation according to the netlist.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsun-Yu YANG, Ren-Hong FU, Chin-Cheng KUO, Jui-Feng KUAN
  • Publication number: 20240387543
    Abstract: The proposed L-shaped field effect transistor comprises a horizontal FET and a vertical FET, wherein one end of the former is in contact with one end of the latter. Thus, the gates (or gate channels) of the two FETs can be separated by a distance so as to reduce mutual interference and simplify fabrication. When the two transistors are made of different materials, the contact area therebetween is small and the gates (or gate channels) of the two FETs are separated by a distance. Thus, the negative effect of interface defects close to the contact area can be reduced. To be compared to planar complementary FET (even FinFET and GAAFET), the proposed L-shaped FET can occupy a similar wafer area and have a similar overall thickness after subsequent metallization.
    Type: Application
    Filed: May 7, 2024
    Publication date: November 21, 2024
    Inventors: YEONG-HER WANG, CHIN-CHENG HSIEH, CHIUNG-YI YANG, DARSEN DUANE LU, YAO-JEN LEE
  • Patent number: 12147119
    Abstract: An electronic device is provided. The electronic device includes a frame, a backlight module, a working panel, and a spacer. The backlight module is disposed in the frame. The working panel is disposed on the frame. The spacer is disposed between the frame and the working panel. At least a portion of the working panel and at least a portion of the spacer are in direct contact with an adhesive.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 19, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Wen-Cheng Huang, Ting-Sheng Chen, Chia-Chun Yang, Chin-Cheng Kuo
  • Patent number: 12126675
    Abstract: A distributed computing system has one or more clusters each including compute nodes connected by a cluster network and executing microservices in respective containers organized into pods. The system includes application slice components (routers, slice gateways) distributed among the clusters to define and operate application slices each providing application slice services for respective sets of pods distributed among the clusters. Each slice gateway provides an interface between local pods of the application slice and remote pods of the application slice on a respective different cluster. Each slice is associated with namespaces, network policies and resource quotas for the applications onboarded on the slice. The slice routers and slice gateways for a given application slice form a respective slice-specific overlay network providing cross-cluster network services including service discovery and traffic forwarding with isolation from other application slices that co-reside on the clusters.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: October 22, 2024
    Assignee: Avesha, Inc.
    Inventors: Raj Nair, Prabhudev Navali, Sudhir Halbhavi, Chin-Cheng Wu, Eric Peterson, Prasad Dorbala