Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A semiconductor structure including a first substrate, a first dielectric layer, a first oxygen doped carbide (ODC) bonding layer, a second substrate, a second dielectric layer, and a second ODC bonding layer is provided. The first dielectric layer is located on the first substrate. The first ODC bonding layer is located on the first dielectric layer. The second dielectric layer is located on the second substrate. The second ODC bonding layer is located on the second dielectric layer. The first ODC bonding layer and the second ODC bonding layer are bonded to each other.

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

Abstract: A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.

Abstract: A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material.

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part . The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material.