Patents by Inventor Chin-Chiang Chang
Chin-Chiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240388288Abstract: A device including an inverter circuit, a hysteresis control circuit, and a high-side input level shifter. The inverter circuit having an output and including at least two series connected PMOS transistors connected, at the output, in series to at least two series connected NMOS transistors. The hysteresis control circuit coupled to the output to provide feedback to the at least two series connected PMOS transistors and to the at least two series connected NMOS transistors. The high-side input level shifter connected to gates of the at least two PMOS transistors and configured to shift a low level of an input signal to a higher level and provide the higher level to one or more of the gates of the at least two PMOS transistors.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Inventors: Yung-Shun Chen, Chin-Chiang Chang, Yung-Chow Peng
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Patent number: 11869831Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.Type: GrantFiled: August 30, 2021Date of Patent: January 9, 2024Assignee: MEDIATEK INC.Inventors: Chin-Chiang Chang, Yin-Fa Chen, Shih-Chin Lin
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Publication number: 20240006278Abstract: A multi-die QFN hybrid package includes a carrier having flip-chip leads and wire-bonding leads. A first die and a second die are mounted on the flip-chip leads, respectively, in a flip-chip manner. The first die is spaced apart from the second die. A third die is stacked over the first die and the second die. The third die is electrically connected to the wire-bonding leads around the first die and the second die through bond wires. A mold cap encapsulates the first die, the second die, the third die, the bond wires, and partially encapsulates the carrier. The flip-chip leads and the wire-bonding leads are exposed from a bottom mold cap surface.Type: ApplicationFiled: May 23, 2023Publication date: January 4, 2024Applicant: MEDIATEK INC.Inventors: Hsin-Long Chen, Chin-Chiang Chang
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Publication number: 20220328394Abstract: A three-dimensional pad structure includes a substrate; a pad disposed on the substrate, wherein a perimeter of the pad is covered with a solder mask; and at least one conductive pillar protruding from a top surface of the pad.Type: ApplicationFiled: March 9, 2022Publication date: October 13, 2022Applicant: MEDIATEK INC.Inventor: Chin-Chiang Chang
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Publication number: 20220115303Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.Type: ApplicationFiled: August 30, 2021Publication date: April 14, 2022Applicant: MEDIATEK INC.Inventors: Chin-Chiang Chang, Yin-Fa Chen, Shih-Chin Lin
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Patent number: 11264309Abstract: A semiconductor package includes at least one die attach pad of a leadframe, at least one semiconductor die mounted on the at least one die attach pad; and a plurality of lead terminals disposed around the at least one die attach pad and electrically connected to respective input/output (I/O) pads on the at least one semiconductor die through a plurality of bond wires. The plurality of lead terminals comprises first lead terminals, second lead terminals, and third lead terminals, which are arranged in triple row configuration along at least one side of the semiconductor package. Each of the first lead terminals, second lead terminals, and third lead terminals has an exposed base metal on a cut end thereof.Type: GrantFiled: May 6, 2020Date of Patent: March 1, 2022Assignee: MEDIATEK INC.Inventor: Chin-Chiang Chang
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Publication number: 20200402893Abstract: A semiconductor package includes at least one die attach pad of a leadframe, at least one semiconductor die mounted on the at least one die attach pad; and a plurality of lead terminals disposed around the at least one die attach pad and electrically connected to respective input/output (I/O) pads on the at least one semiconductor die through a plurality of bond wires. The plurality of lead terminals comprises first lead terminals, second lead terminals, and third lead terminals, which are arranged in triple row configuration along at least one side of the semiconductor package. Each of the first lead terminals, second lead terminals, and third lead terminals has an exposed base metal on a cut end thereof.Type: ApplicationFiled: May 6, 2020Publication date: December 24, 2020Inventor: Chin-Chiang Chang
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Patent number: 10037936Abstract: A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires connecting the semiconductor die to the carrier substrate, an insulating material coated on the bonding wires, and a molding compound covering the top surface and encapsulating the semiconductor die, the plurality of bonding wires, and the insulating material.Type: GrantFiled: June 8, 2016Date of Patent: July 31, 2018Assignee: MediaTek Inc.Inventors: Shiann-Tsong Tsai, Hsueh-Te Wang, Chin-Chiang Chang
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Patent number: 9905515Abstract: The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.Type: GrantFiled: April 15, 2015Date of Patent: February 27, 2018Assignee: MediaTek Inc.Inventors: Chin-Chiang Chang, Tao Cheng
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Patent number: 9837595Abstract: The invention provides a portable electronic system. The portable electronic system includes a semiconductor package. The semiconductor package includes a substrate. A semiconductor die is coupled to the substrate. A thermoelectric device chip is disposed close to the semiconductor die, coupled to the substrate. The thermoelectric device chip is configured to detect a heat energy generated from the semiconductor die and to convert the heat energy into a recycled electrical energy. A power system is coupled to the semiconductor package, configured to store the recycled electrical energy.Type: GrantFiled: May 20, 2015Date of Patent: December 5, 2017Assignee: MEDIATEK INC.Inventors: Long-Kun Yu, Chin-Chiang Chang, Chia-Wei Chi, Chia-Feng Yeh, Tai-Yu Chen
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Publication number: 20170125327Abstract: A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires connecting the semiconductor die to the carrier substrate, an insulating material coated on the bonding wires, and a molding compound covering the top surface and encapsulating the semiconductor die, the plurality of bonding wires, and the insulating material.Type: ApplicationFiled: June 8, 2016Publication date: May 4, 2017Inventors: Shiann-Tsong Tsai, Hsueh-Te Wang, Chin-Chiang Chang
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Publication number: 20160343929Abstract: The invention provides a portable electronic system. The portable electronic system includes a semiconductor package. The semiconductor package includes a substrate. A semiconductor die is coupled to the substrate. A thermoelectric device chip is disposed close to the semiconductor die, coupled to the substrate. The thermoelectric device chip is configured to detect a heat energy generated from the semiconductor die and to convert the heat energy into a recycled electrical energy. A power system is coupled to the semiconductor package, configured to store the recycled electrical energy.Type: ApplicationFiled: May 20, 2015Publication date: November 24, 2016Inventors: Long-Kun YU, Chin-Chiang CHANG, Chia-Wei CHI, Chia-Feng YEH, Tai-Yu CHEN
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Patent number: 9319616Abstract: An audio/video (A/V) display system comprising a display and a peripheral device connected to the display. The display is capable of displaying a user interface. The peripheral device transmits raw data of the peripheral device to the display. The display enables an option corresponding to the peripheral device in the user interface after receiving the raw data of the peripheral device. Both the display and the peripheral device are controlled by a control device.Type: GrantFiled: March 13, 2013Date of Patent: April 19, 2016Assignee: AmTRAN TECHNOLOGY CO., LTDInventors: Chin-Chiang Chang, Kuang-Cheng Chao, Wei-Wen Mai, Chien-Cheng Lin, Min-I Chen, Wen-Kang Wei
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Publication number: 20160043040Abstract: The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.Type: ApplicationFiled: April 15, 2015Publication date: February 11, 2016Inventors: Chin-Chiang Chang, Tao Cheng
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Patent number: 8743293Abstract: An audio/video system includes a display having a plurality of input sources and a first peripheral device connected to one of the input sources. The display provides a user interface for receiving a switching command for switching current input source of the display among the input sources from a user, and the display automatically generates a first standby command to the first peripheral device when the received switching command is not switching the current input source to the input source corresponding to the first peripheral device.Type: GrantFiled: March 4, 2013Date of Patent: June 3, 2014Assignee: AmTran Technology Co., LtdInventors: Chin-Chiang Chang, Kuang-Cheng Chao, Wei-Wen Mai, Chien-Cheng Lin, Min-I Chen, Wen-Kang Wei
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Publication number: 20140132838Abstract: An audio/video system includes a display having a plurality of input sources and a first peripheral device connected to one of the input sources. The display provides a user interface for receiving a switching command for switching current input source of the display among the input sources from a user, and the display automatically generates a first standby command to the first peripheral device when the received switching command is not switching the current input source to the input source corresponding to the first peripheral device.Type: ApplicationFiled: March 4, 2013Publication date: May 15, 2014Applicant: AMTRAN TECHNOLOGY CO., LTDInventors: Chin-Chiang Chang, Kuang-Cheng Chao, Wei-Wen Mai, Chien-Cheng Lin, Min-I Chen, Wen-Kang Wei
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Publication number: 20140132839Abstract: An audio/video (A/V) display system comprising a display and a peripheral device connected to the display. The display is capable of displaying a user interface. The peripheral device transmits raw data of the peripheral device to the display. The display enables an option corresponding to the peripheral device in the user interface after receiving the raw data of the peripheral device. Both the display and the peripheral device are controlled by a control device.Type: ApplicationFiled: March 13, 2013Publication date: May 15, 2014Applicant: AmTRAN TECHNOLOGY CO., LTDInventors: Chin-Chiang Chang, Kuang-Cheng Chao, Wei-Wen Mai, Chien-Cheng Lin, Min-I Chen, Wen-Kang Wei