Patents by Inventor Chin-Chih Chang
Chin-Chih Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996375Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.Type: GrantFiled: February 22, 2023Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu, Kun-Tong Tsai, Hung-Chih Chen
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Patent number: 11996630Abstract: An antenna structure includes a ground element, a first radiation element, a second radiation element, a third radiation element, and a nonconductive support element. The first radiation element is coupled to a first grounding point on the ground element. The second radiation element has a feeding point. The second radiation element is adjacent to the first radiation element. The third radiation element is coupled to a second grounding point on the ground element. The third radiation element is adjacent to the second radiation element. The first radiation element, the second radiation element, and the third radiation element are disposed on the nonconductive support element. The second radiation element is at least partially surrounded by the first radiation element. The third radiation element is at least partially surrounded by the second radiation element.Type: GrantFiled: September 2, 2022Date of Patent: May 28, 2024Assignee: QUANTA COMPUTER INC.Inventors: Yu-Chen Zhao, Chung-Ting Hung, Chin-Lung Tsai, Ying-Cong Deng, Kuan-Hsien Lee, Yi-Chih Lo, Kai-Hsiang Chang, Chun-I Cheng, Yan-Cheng Huang
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Patent number: 11971659Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.Type: GrantFiled: September 26, 2019Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chih Ho, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20240126170Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation, the selectively exposed photoresist layer is developed to form a pattern in the photoresist layer. The photoresist composition includes a polymer including monomer units with photocleaving promoters, wherein the photocleaving promoters are one or more selected from the group consisting of living free radical polymerization chain transfer agents, electron withdrawing groups, bulky two dimensional (2-D) or three dimensional (3-D) organic groups, N-(acyloxy)phthalimides, and electron stimulated radical generators.Type: ApplicationFiled: May 22, 2023Publication date: April 18, 2024Inventors: Chun-Chih HO, Chin-Hsiang Lin, Ching-Yu Chang
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Publication number: 20240118618Abstract: A method of manufacturing a semiconductor device includes forming a first layer having an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing polymer having pendant acid groups or pendant photoacid generator groups. The forming a second layer includes: forming a layer of a composition including a silicon-based polymer and a material containing an acid group or photoacid generator group over the first layer, floating the material containing an acid group or photoacid generator group over the silicon-based polymer, and reacting the material containing an acid group or photoacid generator group with the silicon-based polymer to form an upper second layer including a silicon-based polymer having pendant acid groups or pendant photoacid generator groups overlying a lower second layer comprising the silicon-based polymer. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.Type: ApplicationFiled: April 12, 2023Publication date: April 11, 2024Inventors: Chun-Chih HO, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Publication number: 20240103375Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Chih HO, Ching-Yu CHANG, Chin-Hsiang LIN
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Patent number: 11943936Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.Type: GrantFiled: August 12, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Der Chih, May-Be Chen, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Wen Zhang Lin, Chrong Jung Lin, Ya-Chin King, Chieh Lee, Wang-Yi Lee
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Patent number: 11276677Abstract: Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.Type: GrantFiled: February 12, 2020Date of Patent: March 15, 2022Assignee: Cadence Design Systems, Inc.Inventors: Liqun Deng, Pinhong Chen, Richard M. Chou, Chin-Chih Chang, Miao Liu, Yufeng Luo