Patents by Inventor Chin-Chih Hsiao

Chin-Chih Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabrication method of packaging substrate
    Patent number: 9455159
    Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 27, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kuan-I Cheng, Cheng-Wen Chiu
  • FABRICATION METHOD OF PACKAGING SUBSTRATE
    Publication number: 20160013074
    Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.
    Type: Application
    Filed: September 25, 2015
    Publication date: January 14, 2016
    Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kuan-I Cheng, Cheng-Wen Chiu
  • Packaging substrate and fabrication method thereof
    Patent number: 9171741
    Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 27, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kaun-i Cheng, Cheng-Wen Chiu
  • PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF
    Publication number: 20130115738
    Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.
    Type: Application
    Filed: August 3, 2012
    Publication date: May 9, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kaun-i Cheng, Cheng-Wen Chiu