Patents by Inventor Chin-Chin Tsai
Chin-Chin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030297Abstract: An integrated structure of semiconductor devices having a shared contact plug includes: a first device, a second device and a shared contact plug. The first device includes a first gate having a conduction region, two spacer regions and a protection region. The two spacer regions overlay and are connected with two ends of the conductive region, respectively. The protection region overlays and is connected with the spacer region located outside a shared side of the conductive region. The second device includes a shared region, wherein the shared region is located in a semiconductor layer which is located below and outside the protection region. The shared contact plug is formed on and in contact with the conductive region and the shared region. The first gate is electrically connected with the shared region through the shared contact plug, wherein the shared contact plug overlays and is connected with the protection region.Type: ApplicationFiled: May 9, 2023Publication date: January 25, 2024Inventors: Chin-Chin Tsai, Han-Chung Tai, Yong-Zhong Hu
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Publication number: 20230402327Abstract: A manufacturing method of an integrated structure of semiconductor devices having split gates includes: forming a first silicon nitride layer covering a low voltage device and a high voltage device; etching back the first silicon nitride layer by an etching process step to form a residue silicon nitride region between two adjacent low voltage gates; forming a silicon oxide layer, a second silicon nitride layer, and a metal layer; forming two split gates by an etching process step; forming a contact etch stop layer (CESL); etching the CESL by an etching process step to form plural contacts in the CESL, wherein the contact between the two adjacent low voltage gates exposes at least part of a top surface of a common low voltage source on a substrate; and forming plural conductive plugs in the plural contacts respectively, wherein each of the conductive plug fills up the corresponding contact.Type: ApplicationFiled: August 30, 2022Publication date: December 14, 2023Inventor: Chin-Chin Tsai
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Patent number: 11777007Abstract: A method for fabricating memory device is provided. The method comprises forming a cell structure on a substrate, wherein the cell structure comprises a first gate structure and a second gate structure disposed on a substrate and an insulating layer in contact between the first gate structure and the second gate structure, wherein the first gate structure and the second gate structure are planarized and the first gate structure is for storing charges. Further, the first gate structure and the second gate structure are patterned to have a shallow indent above the insulating layer. An isolation structure is formed in the shallow indent to have a shallow indent isolation.Type: GrantFiled: March 17, 2021Date of Patent: October 3, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventor: Chin-Chin Tsai
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Publication number: 20230238242Abstract: A polysilicon-insulator-polysilicon (PIP) structure includes: a first polysilicon region formed on a substrate; a first insulation region formed outside one side of the first polysilicon region and adjoined to the first polysilicon region in a horizontal direction; and a second polysilicon region formed outside one side of the first insulation region. The first polysilicon region, the first insulation region and the second polysilicon region are adjoined in sequence in the horizontal direction. The second polysilicon region is formed outside the first insulation region by a first self-aligned process step, and the first insulation region is formed outside the first polysilicon region by a second self-aligned process step.Type: ApplicationFiled: September 19, 2022Publication date: July 27, 2023Inventors: Chin-Chin Tsai, Yong-Zhong Hu
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Patent number: 11348805Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.Type: GrantFiled: October 9, 2020Date of Patent: May 31, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
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Publication number: 20210202707Abstract: A method for fabricating memory device is provided. The method comprises forming a cell structure on a substrate, wherein the cell structure comprises a first gate structure and a second gate structure disposed on a substrate and an insulating layer in contact between the first gate structure and the second gate structure, wherein the first gate structure and the second gate structure are planarized and the first gate structure is for storing charges. Further, the first gate structure and the second gate structure are patterned to have a shallow indent above the insulating layer. An isolation structure is formed in the shallow indent to have a shallow indent isolation.Type: ApplicationFiled: March 17, 2021Publication date: July 1, 2021Applicant: United Microelectronics Corp.Inventor: Chin-Chin Tsai
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Patent number: 10991806Abstract: A structure of memory device is provided. The structure of memory device includes a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges. In addition, a second gate structure is disposed on the substrate. An insulating layer is in contact between the first gate structure and the second gate structure. An isolation structure integrated with the insulating layer is between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure. The isolation structure provides an isolation distance between the first gate structure and the second gate structure.Type: GrantFiled: May 9, 2019Date of Patent: April 27, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventor: Chin-Chin Tsai
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Patent number: 10916555Abstract: A structure of memory cell includes a memory gate structure, disposed on a substrate, wherein the substrate has an indent region aside the memory gate structure. A selection gate structure is disposed on the substrate at the indent region aside the memory gate structure. A first insulation layer is at least disposed between the memory gate structure and selection gate structure.Type: GrantFiled: January 31, 2019Date of Patent: February 9, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventor: Chin-Chin Tsai
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Publication number: 20210028025Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.Type: ApplicationFiled: October 9, 2020Publication date: January 28, 2021Applicant: United Microelectronics Corp.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
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Patent number: 10847378Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.Type: GrantFiled: November 1, 2018Date of Patent: November 24, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
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Publication number: 20200357891Abstract: A structure of memory device is provided. The structure of memory device includes a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges. In addition, a second gate structure is disposed on the substrate. An insulating layer is in contact between the first gate structure and the second gate structure. An isolation structure integrated with the insulating layer is between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure. The isolation structure provides an isolation distance between the first gate structure and the second gate structure.Type: ApplicationFiled: May 9, 2019Publication date: November 12, 2020Applicant: United Microelectronics Corp.Inventor: Chin-Chin Tsai
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Publication number: 20200251482Abstract: A structure of memory cell includes a memory gate structure, disposed on a substrate, wherein the substrate has an indent region aside the memory gate structure. A selection gate structure is disposed on the substrate at the indent region aside the memory gate structure. A first insulation layer is at least disposed between the memory gate structure and selection gate structure.Type: ApplicationFiled: January 31, 2019Publication date: August 6, 2020Applicant: United Microelectronics Corp.Inventor: Chin-Chin Tsai
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Publication number: 20200144072Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.Type: ApplicationFiled: November 1, 2018Publication date: May 7, 2020Inventors: CHIA-HUNG CHEN, YU-HUANG YEH, CHUAN-FU WANG, CHIN-CHIN TSAI
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Publication number: 20080068535Abstract: A liquid crystal (LC) electro-optics (EO) film with particles having a large surface area is provided, which includes an EO substrate with an electrode layer, an LC mixture coating layer and a conductive polymer layer. The LC mixture coating layer is located on the surface of the EO substrate and contains sponge particles and liquid crystal. The LC mixture coating layer is covered with the conductive polymer layer that does not contact with the electrode layer.Type: ApplicationFiled: December 20, 2006Publication date: March 20, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chin-Chin Tsai, Wei-Hsin Hou
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Publication number: 20040080070Abstract: A method of manufacturing polymeric foam. The invention is related to a method of manufacturing polymeric foam by allowing supercritical fluids to diffuse into polymeric material placed in a mold directly through the mold to impregnate the polymeric material.Type: ApplicationFiled: September 25, 2003Publication date: April 29, 2004Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsin-Chu Liu, Hsi-Hsin Shih, Chin-Chin Tsai, Chien-Tsung Wu, Wen-Bing Liu
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Patent number: 6673286Abstract: A method of making a porous biodegradable polymer is disclosed, which comprises (a) placing a biodegradable polymer and a solvent in a chamber; (b) adding a supercritical fluid to the chamber and maintaining the chamber at a predetermined temperature for a sufficient period of time to allow the supercritical fluid to dissolve into the biodegradable polymer with the help of the solvent; and (c) venting the supercritical fluid and the solvent by reducing the pressure in the chamber, thereby obtaining a porous biodegradable polymer.Type: GrantFiled: September 4, 2001Date of Patent: January 6, 2004Assignee: Industrial Technology Research InstituteInventors: Hsi-Hsin Shih, Kuang-Rong Lee, Huey-Min Lai, Chin-Chin Tsai, Yuan-Chia Chang
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Patent number: 6670454Abstract: The present invention relates to crosslinking of porous materials made of biodegradable polymers. The method comprises: (a) placing a porous biodegradable polymer in a chamber; (b) introducing a supercritical fluid containing a crosslinking agent into the chamber to effect crosslinking of the porous biodegradable polymer; and optionally (c) introducing a pure supercritical into the chamber to wash the crosslinked polymer until the crosslinking agent is substantially removed from the polymer.Type: GrantFiled: November 1, 2001Date of Patent: December 30, 2003Assignee: Industrial Technology Research InstituteInventors: Huey-Min Lai, Kuang-Rong Lee, Chin-Chin Tsai, Hsi-Hsin Shih, Yuan-Chia Chang
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Publication number: 20030153638Abstract: The present invention relates to crosslinking of porous materials made of biodegradable polymers. The method comprises: (a) placing a porous biodegradable polymer in a chamber; (b) introducing a supercritical fluid containing a crosslinking agent into the chamber to effect crosslinking of the porous biodegradable polymer; and optionally (c) introducing a pure supercritical into the chamber to wash the crosslinked polymer until the crosslinking agent is substantially removed from the polymer.Type: ApplicationFiled: November 1, 2001Publication date: August 14, 2003Applicant: Industrial Technology Research InstituteInventors: Huey-Min Lai, Kuang-Rong Lee, Chin-Chin Tsai, Hsi-Hsin Shih, Yuan-Chia Chang
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Publication number: 20030072790Abstract: A biodegradable porous device for tissue engineering is disclosed, which comprises (A) a porous polymeric scaffold comprising a co-continuous phase of a first biodegradable polymer and a second biodegradable polymer which are incompatible with each other, wherein the first biodegradable polymer contains a continuous network of large, interconnected pores, and the second biodegradable polymer contains small, partially interconnected pores; (B) a biodegradable polymer fiber dispersed in, and compatible with the matrix of the first biodegradable polymer; and optionally (C) an active ingredient provided in the polymeric scaffold.Type: ApplicationFiled: October 16, 2001Publication date: April 17, 2003Applicant: Industrial Technology Research InstituteInventors: Chin-Chin Tsai, Hsi-Hsin Shih, Huey-Min Lai
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Publication number: 20030064156Abstract: A method of making a porous biodegradable polymer is disclosed, which comprises (a) placing a biodegradable polymer and a solvent in a chamber; (b) adding a supercritical fluid to the chamber and maintaining the chamber at a predetermined temperature for a sufficient period of time to allow the supercritical fluid to dissolve into the biodegradable polymer with the help of the solvent; and (c) venting the supercritical fluid and the solvent by reducing the pressure in the chamber, thereby obtaining a porous biodegradable polymer.Type: ApplicationFiled: September 4, 2001Publication date: April 3, 2003Applicant: Industrial Technology Research InstituteInventors: Hsi-Hsin Shih, Kuang-Rong Lee, Huey-Min Lai, Chin-Chin Tsai, Yuan-Chia Chang