Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.

Abstract: Provided is an inductor structure and manufacturing method thereof, including forming an inductance coil in a semiconductor packaging carrier plate and disposing a patterned magnetic conductive layer in the inductance coil. Therefore, a patterned build-up wiring method is used to form a magnetic material in the carrier plate, thereby improving electrical characteristics of the inductor.

Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: A method includes: obtaining impact values for characteristic conditions; selecting training data subsets respectively from training data sets according to the impact values; obtaining a candidate model and an evaluation value based on the training data subsets; supplementing the training data subsets according to the impact values; obtaining another candidate model and another evaluation value based on training data subsets thus supplemented; repeating the step of supplementing the training data subset, and the step of obtaining another candidate model and another evaluation value based on the training data subsets thus supplemented; and selecting one of the candidate models as a prediction model based on the evaluation values.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Abstract: A device may include a display that display an image frame that is divided into adjustable regions having respective resolutions based on compensated image data. The device may also include image processing circuitry to generate the compensated image data by applying gains that compensate for burn-in related aging of pixels of the display. The gains are based on an aggregation of history updates indicative of estimated amounts of aging associated with pixel utilization. The circuitry may generate a history update by obtaining boundary data indicative of the boundaries between the adjustable regions, determining an estimated amount of aging, and dynamically resampling the estimated amount of aging by resampling a portion of the estimated amount of aging corresponding to an adjustable region by a factor and resampling of a different portion of the estimated amount of aging corresponding to another adjustable region by a different factor based on the boundary data.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: The present disclosure relates to systems and methods for real and virtual object interactions in augmented reality environments are disclosed. The system comprises areal object detection module to receive multiple image pixels and the corresponding depths of at least one initiative object, a real object recognition module to determine a shape, a position, and a movement of the initiative object; a virtual object display module to display a virtual target object, a collision module to determine whether the at least one initiative object collides into a virtual target object and, an interaction module for determining an action responding to an event based on at least one of an object recognition determination from the real object recognition module, a collision determination from the collision module, and a type of the virtual target object.

Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.

Abstract: A device may include a display that display an image frame that is divided into adjustable regions having respective resolutions based on compensated image data. The device may also include image processing circuitry to generate the compensated image data by applying gains that compensate for burn-in related aging of pixels of the display. The gains are based on an aggregation of history updates indicative of estimated amounts of aging associated with pixel utilization. The circuitry may generate a history update by obtaining boundary data indicative of the boundaries between the adjustable regions, determining an estimated amount of aging, and dynamically resampling the estimated amount of aging by resampling a portion of the estimated amount of aging corresponding to an adjustable region by a factor and resampling of a different portion of the estimated amount of aging corresponding to another adjustable region by a different factor based on the boundary data.

Abstract: A device may include a display for displaying an image frame based on warped image data and image processing circuitry to generate the warped image data by warping input image data to account for one or more distortions associated with displaying the image. The image processing circuitry may include a two-stage cache architecture having an first cache and an second cache and warp the input image data by generating mapping data indicative of a warp between the input image space and the output image space and fetching the input image data to populate the first cache. Warping may also include populating the second cache with a grouping of pixel values from the first cache that are selected according to a sliding window that traverses the first cache based on the mapping data and interpolating between pixel values of the grouping to generate pixel values of the warped image data.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: A battery balancing system includes a voltage sensing unit, a characteristic voltage selector and a control unit. The voltage sensing unit senses a battery voltage of each of the batteries connected in series in a battery group and generates corresponding battery voltage sensing signals. The characteristic voltage selector generates a characteristic voltage according to the battery voltage sensing signals. The control unit compares the characteristic voltage with a threshold voltage in a balance operation mode, to adaptively adjust the threshold voltage, and compares the battery voltage sensing signal with the adjusted threshold voltage to generate a battery balancing command, thereby executing a charge removal balancing command or a charge supplying balancing command on the corresponding battery, or thereby cease executing the charge removal balancing command or cease executing the charge supplying balancing command on the corresponding battery.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.

Abstract: A cell region of a semiconductor device, the cell region including: components (representing a first circuit) including alpha info conductors and dummy conductors which are substantially collinear correspondingly with reference tracks, regarding the first circuit, the alpha info conductors beipng correspondingly for one or more input and/or output signals, or one or more internal signals, and for a majority of the reference tracks, first ends correspondingly of the alpha info conductors or the dummy conductors being aligned and proximal to a first side of the cell region; a first alpha info conductor being on a first reference track and being an intra-cell conductor which does not extend beyond the first side nor a second side of the cell region; and a portion of a first beta info conductor of a second circuit (represented by components of an external cell region) being on the first reference track.

Abstract: A flow meter includes a meter body and a pressure sensor. The meter body has a liquid impact surface, a sensing surface opposite to the liquid impact surface, and a mounting hole extending from the sensing surface toward the liquid impact surface. The mounting hole is a blind hole. The pressure sensor is mounted in the mounting hole, and has a resistance value that can be measured and that can be changed correspondingly with a change in liquid pressure caused by a change in flow rate. A device for producing an active hydroxyl free radical solution is also disclosed.

Abstract: The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.