Patents by Inventor Chin-Chou Liu

Chin-Chou Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210365621
    Abstract: The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Inventors: CHIN-CHOU LIU, YI-KUANG LEE, LIE-SZU JUANG
  • Publication number: 20210351110
    Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Inventors: Noor E.V. Mohamed, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
  • Publication number: 20210335668
    Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 28, 2021
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Publication number: 20210320072
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu LEE, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
  • Patent number: 11138360
    Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Hui-Zhong Zhuang, Meng-Hsueh Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Publication number: 20210305213
    Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventors: Chih-Lin CHEN, Hui-Yu LEE, Fong-Yuan CHANG, Po-Hsiang HUANG, Chin-Chou LIU
  • Publication number: 20210294957
    Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Pin-Dai SUE, Po-Hsiang HUANG, Fong-Yuan CHANG, Chi-Yu LU, Sheng-Hsiung CHEN, Chin-Chou LIU, Lee-Chung LU, Yen-Hung LIN, Li-Chun TIEN, Yi-Kan CHENG
  • Patent number: 11120186
    Abstract: The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Chou Liu, Yi-Kuang Lee, Lie-Szu Juang
  • Publication number: 20210257156
    Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 19, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ka Fai CHANG, Chin-Chou LIU, Fong-Yuan CHANG, Hui Yu LEE, Yi-Kan CHENG
  • Patent number: 11094608
    Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 17, 2021
    Inventors: Po-Hsiang Huang, Chin-Chou Liu, Chin-Her Chien, Fong-yuan Chang, Hui Yu Lee
  • Patent number: 11088084
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
  • Patent number: 11081426
    Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Noor E. V. Mohamed, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
  • Patent number: 11075116
    Abstract: The present disclosure relates to an integrated antenna structure. The integrated antenna structure includes a radiator and a ground plane disposed between a semiconductor substrate and the radiator. A conductive structure is separated from the ground plane by the semiconductor substrate. The conductive structure is electrically coupled to the ground plane. The semiconductor substrate has a thickness of less than approximately 100 microns.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jr Huang, William Wu Shen, Chin-Her Chien, Chin-Chou Liu, Yun-Han Lee
  • Patent number: 11043473
    Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Lin Chen, Chin-Chou Liu, Fong-Yuan Chang, Hui-Yu Lee, Po-Hsiang Huang
  • Publication number: 20210173998
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor JAN, Yi-Kan CHENG, Hsiu-Chuan SHU
  • Patent number: 11030372
    Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pin-Dai Sue, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Po-Hsiang Huang, Yi-Kan Cheng, Chi-Yu Lu
  • Publication number: 20210110097
    Abstract: A method (of generating a layout diagram) includes: generating a shell including wiring patterns in a first layer of metallization, the wiring patterns having long axes which are substantially aligned with corresponding tracks that extend in a first direction, the wiring patterns having a default arrangement which has, relative to the corresponding tracks, a first amount of free space; and refining the shell into a cell, the refining including selectively shrinking, in the first direction, one or more of the wiring patterns resulting in a second amount of free space, the second amount being greater than the first amount, increasing, in the first direction, one or more chosen ones of the wiring patterns (chosen patterns), and backfilling the second amount of free space with one or more of at least one dummy pattern or at least one wiring pattern.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Sheng-Hsiung CHEN, Po-Hsiang HUANG
  • Publication number: 20210097222
    Abstract: The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.
    Type: Application
    Filed: April 13, 2020
    Publication date: April 1, 2021
    Inventors: CHIN-CHOU LIU, YI-KUANG LEE, LIE-SZU JUANG
  • Publication number: 20210082816
    Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Fong-yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
  • Publication number: 20210082960
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu