Abstract: Disclosed herein is an electrophoretic display, which includes a first substrate, an electrophoretic layer, a second substrate, a stress controlling layer and an adhesive layer. The first substrate includes at least one active device and at least one pixel electrode electrically coupled to the active device. The electrophoretic layer is disposed above the pixel electrode. The second substrate is disposed above the electrophoretic layer. The stress controlling layer is formed on a lower surface of the second substrate. The adhesive layer is disposed between the surface stressed layer and the electrophoretic layer, and is in contact with the stress controlling layer and the electrophoretic layer. The adhesion between the stress controlling layer and the adhesive layer is about 75% to 125% of the adhesion between the electrophoretic layer and the adhesive layer.

Abstract: Disclosed herein is an electrophoretic display, which includes a first substrate, an electrophoretic layer, a second substrate, a stress controlling layer and an adhesive layer. The first substrate includes at least one active device and at least one pixel electrode electrically coupled to the active device. The electrophoretic layer is disposed above the pixel electrode. The second substrate is disposed above the electrophoretic layer. The stress controlling layer is formed on a lower surface of the second substrate. The adhesive layer is disposed between the surface stressed layer and the electrophoretic layer, and is in contact with the stress controlling layer and the electrophoretic layer. The adhesion between the stress controlling layer and the adhesive layer is about 75% to 125% of the adhesion between the electrophoretic layer and the adhesive layer.

Abstract: An organic thin film transistor including a substrate, a gate, a gate insulator, an adhesive layer, a metal nano-particle layer and an organic semiconductor layer is provided. The gate is disposed on the substrate. The gate insulator is disposed on the gate and the substrate. The adhesive layer is disposed on the gate insulator. Besides, the adhesive layer has a hydrophobic surface above the gate and a first hydrophilic surface and a second hydrophilic surface on two sides of the hydrophobic surface. A surface of the metal nano-particle layer is modified by a hydrophilic group, and the metal nano-particle layer is disposed on the first and the second hydrophilic surfaces of the adhesive layer as a source and a drain, respectively. The organic semiconductor layer is disposed on the hydrophobic surface of the adhesive layer and on the metal nano-particle layer.

Abstract: A method of fabricating a pixel structure is provided. First, a semiconductor material layer and a first conductive layer are sequentially formed on a substrate. Next, a first patterned photoresist layer with a fillister is formed on the first conductive layer by a first mask. A semiconductor layer, a drain, and a source are formed by the first patterned photoresist layer. After removing the first patterned photoresist layer, a dielectric material layer covering the source, the drain, and the semiconductor layer is formed. A second conductive layer is formed on the dielectric material layer. Then, a second patterned photoresist layer with a salient is formed on the second conductive layer by a second mask. A gate and a dielectric layer are formed by the second patterned photoresist layer. After removing the second patterned photoresist layer, a pixel electrode electrically connected to the drain is formed above the substrate.

Abstract: A manufacturing method of a TFT is provided. A polysilicon island, a gate insulating layer and a gate are sequentially formed on a substrate. LDD regions are formed in the polysilicon island below two sides of the gate, while the polysilicon island below the gate is a channel region. A metal oxidation process is performed to form a gate oxidation layer on the gate. A source and a drain are formed in the polysilicon island below two sides of the gate oxidation layer. A dielectric layer is formed on the gate insulating layer. Portions of the dielectric layer and the gate insulating layer are removed to expose a portion of the source and drain, and a patterned dielectric layer and a patterned gate insulating layer are formed. A source and a drain conductive layers electrically respectively connected to the source and the drain are formed on the patterned dielectric layer.

Abstract: A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process.

Abstract: A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process.

Abstract: A thin film transistor including a substrate, a gate, a gate insulator layer, a semiconductor layer, an ohmic contact layer, a source and a drain is provided. The gate is disposed on the substrate while the gate insulator layer is disposed on the substrate and covers the gate. The semiconductor layer is disposed on the gate insulator layer above the gate. The semiconductor layer includes an undoped amorphous silicon layer and a first undoped microcrystalline silicon (?c-Si) layer, wherein the first undoped ?c-Si layer is disposed on the undoped amorphous silicon layer. The ohmic contact layer is disposed on part of the semiconductor layer and the source and the drain are disposed on the ohmic contact layer. Therefore, the thin film transistor has better quality control and electrical characteristics.

Abstract: A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at least disposed on the first dielectric layer above the gate. The source/drain is disposed on the channel layer. The source/drain includes a first barrier layer, a conductive layer and a second barrier layer. The first barrier layer is disposed between the conductive layer and the channel layer. The conductive layer is covered with the first barrier layer and the second barrier layer. The source/drain is covered with the second dielectric layer. Accordingly, the variation of electric characters can be reduced. Moreover, a method for fabricating a thin film transistor is also provided.

Abstract: An organic thin film transistor including a substrate, a gate, a gate insulator, an adhesive layer, a metal nano-particle layer and an organic semiconductor layer is provided. The gate is disposed on the substrate. The gate insulator is disposed on the gate and the substrate. The adhesive layer is disposed on the gate insulator. Besides, the adhesive layer has a hydrophobic surface above the gate and a first hydrophilic surface and a second hydrophilic surface on two sides of the hydrophobic surface. A surface of the metal nano-particle layer is modified by a hydrophilic group, and the metal nano-particle layer is disposed on the first and the second hydrophilic surfaces of the adhesive layer as a source and a drain, respectively. The organic semiconductor layer is disposed on the hydrophobic surface of the adhesive layer and on the metal nano-particle layer.

Abstract: A thin film transistor and a fabrication method thereof are provided. First, a gate is formed on a substrate. Next, a gate insulating layer is formed to cover the gate and then a channel layer is formed on a portion of the gate insulating layer above the gate. Afterwards, a source and a drain are formed on the channel layer. The method of forming the gate includes forming a copper alloy layer containing nitrogen and a copper layer sequentially and then removing a portion of the copper alloy layer containing nitrogen and the copper layer. The source and the drain could be formed by the same fabrication method.

Abstract: A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at least disposed on the first dielectric layer above the gate. The source/drain is disposed on the channel layer. The source/drain includes a first barrier layer, a conductive layer and a second barrier layer. The first barrier layer is disposed between the conductive layer and the channel layer. The conductive layer is covered with the first barrier layer and the second barrier layer. The source/drain is covered with the second dielectric layer. Accordingly, the variation of electric characters can be reduced. Moreover, a method for fabricating a thin film transistor is also provided.

Abstract: Aluminum gate electrode parasitic resistance and capacitance delay suffers performance, and even makes the signal loss to high-resolution and small-size requests for thin film transistor liquid crystal display. An important technology employed in manufacturing thin film transistor is to convert surface of glass substrate into a silicon nitride layer, and subsequently to plate with one of low resistant copper, silver, copper alloy and silver alloy, and finally to form the thin film transistor on the substrate.

Abstract: A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at least disposed on the first dielectric layer above the gate. The source/drain is disposed on the channel layer. The source/drain includes a first barrier layer, a conductive layer and a second barrier layer. The first barrier layer is disposed between the conductive layer and the channel layer. The conductive layer is covered with the first barrier layer and the second barrier layer. The source/drain is covered with the second dielectric layer. Accordingly, the variation of electric characters can be reduced. Moreover, a method for fabricating a thin film transistor is also provided.

Abstract: A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

Abstract: A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

Abstract: A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at least disposed on the first dielectric layer above the gate. The source/drain is disposed on the channel layer. The source/drain includes a first barrier layer, a conductive layer and a second barrier layer. The first barrier layer is disposed between the conductive layer and the channel layer. The conductive layer is covered with the first barrier layer and the second barrier layer. The source/drain is covered with the second dielectric layer. Accordingly, the variation of electric characters can be reduced. Moreover, a method for fabricating a thin film transistor is also provided.