Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Abstract: The invention discloses a display panel, comprising: a first substrate including a display region and a peripheral region adjacent to each other; a plurality of pixel units disposed on the first substrate and located in the display region; a control circuit disposed on the first substrate, located in the peripheral region and electrically connected to the pixel units; a planarization layer disposed on the first substrate, extending from the display region to the peripheral region and covering the pixel units and the control circuit; and a bonding pad disposed on the first substrate and located above the planarization layer; wherein a projection area of the bonding pad on the first substrate and a projection area of the control circuit on the first substrate have an overlapped region.

Abstract: The invention provides a display device and a method of manufacturing a thin film transistor. The method of manufacturing a thin film transistor comprises: (A) providing a substrate; (B) forming a light shielding layer on the substrate, and patterning the light shielding layer to form a patterned light shielding layer; (C) forming a buffer layer on the substrate; (D) forming a semiconductor layer on the substrate, and patterning the semiconductor layer to form a patterned semiconductor layer; (E) forming an insulating layer on the substrate; and (F) forming a conductive layer on the substrate, and patterning the conductive layer to form a patterned conductive layer; wherein the same mask is used for patterning the light shielding layer and the semiconductor layer. Photoelectric effect of the thin film transistor outside the display region can be effectively avoided, while reducing the number of masks in the production process.

Abstract: The invention discloses a display panel, comprising: a first substrate including a display region and a peripheral region adjacent to each other; a plurality of pixel units disposed on the first substrate and located in the display region; a control circuit disposed on the first substrate, located in the peripheral region and electrically connected to the pixel units; a planarization layer disposed on the first substrate, extending from the display region to the peripheral region and covering the pixel units and the control circuit; and a bonding pad disposed on the first substrate and located above the planarization layer; wherein a projection area of the bonding pad on the first substrate and a projection area of the control circuit on the first substrate have an overlapped region.

Abstract: The invention provides a display device and a method of manufacturing a thin film transistor. The method of manufacturing a thin film transistor comprises: (A) providing a substrate; (B) forming a light shielding layer on the substrate, and patterning the light shielding layer to form a patterned light shielding layer; (C) forming a buffer layer on the substrate; (D) forming a semiconductor layer on the substrate, and patterning the semiconductor layer to form a patterned semiconductor layer; (E) forming an insulating layer on the substrate; and (F) forming a conductive layer on the substrate, and patterning the conductive layer to form a patterned conductive layer; wherein the same mask is used for patterning the light shielding layer and the semiconductor layer. Photoelectric effect of the thin film transistor outside the display region can be effectively avoided, while reducing the number of masks in the production process.

Abstract: A method of forming an apparatus comprises forming filled trenches within a semiconductive structure having a well region comprising one or more dopants, the filled trenches extending into the well region and each individually comprising a conductive gate structure and a dielectric liner intervening between the conductive gate structure and the semiconductive structure. A fluorine-doped region is formed at junctions between the well region and additional regions of the semiconductive structure overlying the well region. The additional regions of the semiconductive structure are doped with one or more additional dopants having a different conductivity type than that of the one or more dopants of the well region after forming the fluorine-doped region. The semiconductive structure is annealed after doping the additional regions thereof. Apparatuses, memory devices, and electronic systems also described.

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed.

Abstract: A control device and a control method for equally charging and discharging battery units may prolong life of the battery units of the control device. The control method includes steps of: detecting the battery units to generate measuring parameters; calculating determining parameters; calculating an average value of the determining parameters; selecting one of the battery units according to an operating status of the battery units; calculating a setting parameter; setting a pause time; charging or discharging the selected battery unit after stopping charging or discharging the selected battery unit for the pause time. When the battery units are charged or discharged, an overcharged or over-discharged battery unit may be selected. The selected battery unit may be stopped charging or discharging for the pause time. Therefore, life of the battery units may be prolonged.

Abstract: A method of forming an apparatus comprises forming filled trenches within a semiconductive structure having a well region comprising one or more dopants, the filled trenches extending into the well region and each individually comprising a conductive gate structure and a dielectric liner intervening between the conductive gate structure and the semiconductive structure. A fluorine-doped region is formed at junctions between the well region and additional regions of the semiconductive structure overlying the well region. The additional regions of the semiconductive structure are doped with one or more additional dopants having a different conductivity type than that of the one or more dopants of the well region after forming the fluorine-doped region. The semiconductive structure is annealed after doping the additional regions thereof. Apparatuses, memory devices, and electronic systems also described.

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed.

Abstract: A battery parallel device having a charge path and a discharge path with equal impedances includes at least one first parallel apparatus. The at least one first parallel apparatus has first battery units each having a plurality of first batteries, a first positive connector electrically connected to positive electrodes of the first batteries, a first negative connector electrically connected to negative electrodes of the first batteries, a first positive electrode connector formed on the first positive connector, a first negative electrode connector formed on the first negative connector, first current paths formed between the first positive electrode connector and the positive electrodes, and second current paths formed between the first negative electrode connector and the negative electrodes. A total path length of the first current paths and a total path length of the second current paths corresponding to the same first batteries are equal. Therefore, inrush current may be decreased.

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed.

Abstract: A weldingless cylindrical battery pack device has a first lid body, a second lid body, multiple cylindrical batteries, multiple screwing elements, a first elastic piece, and a second elastic piece. The cylindrical batteries are mounted between the first lid body and the second lid body. The first lid body and the second lid body are screwed together by the screwing elements. Further, the first elastic piece is electronically connected to positive electrodes of the cylindrical batteries, and the second elastic piece is electronically connected to negative electrodes of the cylindrical batteries. The cylindrical batteries do not need to be welded, and the weldingless cylindrical battery pack device may be easily and quickly manufactured.

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed.

Abstract: A control device and a control method for equally charging and discharging battery units may prolong life of the battery units of the control device. The control method includes steps of: detecting the battery units to generate measuring parameters; calculating determining parameters; calculating an average value of the determining parameters; selecting one of the battery units according to an operating status of the battery units; calculating a setting parameter; setting a pause time; charging or discharging the selected battery unit after stopping charging or discharging the selected battery unit for the pause time. When the battery units are charged or discharged, an overcharged or over-discharged battery unit may be selected. The selected battery unit may be stopped charging or discharging for the pause time. Therefore, life of the battery units may be prolonged.

Abstract: A battery parallel device having a charge path and a discharge path with equal impedances includes at least one first parallel apparatus. The at least one first parallel apparatus has first battery units each having a plurality of first batteries, a first positive connector electronically connected to positive electrodes of the first batteries, a first negative connector electronically connected to negative electrodes of the first batteries, a first positive electrode connector formed on the first positive connector, a first negative electrode connector formed on the first negative connector, first current paths formed between the first positive electrode connector and the positive electrodes, and second current paths formed between the first negative electrode connector and the negative electrodes. A total path length of the first current paths and a total path length of the second current paths corresponding to the same first batteries are equal. Therefore, inrush current may be decreased.

Abstract: A weldingless cylindrical battery pack device has a first lid body, a second lid body, multiple cylindrical batteries, multiple screwing elements, a first elastic piece, and a second elastic piece. The cylindrical batteries are mounted between the first lid body and the second lid body. The first lid body and the second lid body are screwed together by the screwing elements. Further, the first elastic piece is electronically connected to positive electrodes of the cylindrical batteries, and the second elastic piece is electronically connected to negative electrodes of the cylindrical batteries. The cylindrical batteries do not need to be welded, and the weldingless cylindrical battery pack device may be easily and quickly manufactured.

Abstract: A touch display panel including an active device array substrate, an opposite substrate and a liquid crystal layer is provided. The active device array substrate includes a first substrate, a black matrix, a touch-sensing device layer, a dielectric layer and an active device array layer. The black matrix is disposed on the first substrate. The touch-sensing device layer is disposed on the first substrate to cover a portion of the black matrix. The dielectric layer covers the touch-sensing device layer. The active device array layer is disposed on the dielectric layer. The touch-sensing device layer and the active device array substrate are located at two opposite sides of the dielectric layer. The liquid crystal layer is disposed between the active device array layer and the opposite substrate. Moreover, a fabricating method of the touch display panel is also provided.

Abstract: A touch display panel including an active device array substrate, an opposite substrate and a liquid crystal layer is provided. The active device array substrate includes a first substrate, a black matrix, a touch-sensing device layer, a dielectric layer and an active device array layer. The black matrix is disposed on the first substrate. The touch-sensing device layer is disposed on the first substrate to cover a portion of the black matrix. The dielectric layer covers the touch-sensing device layer. The active device array layer is disposed on the dielectric layer. The touch-sensing device layer and the active device array substrate are located at two opposite sides of the dielectric layer. The liquid crystal layer is disposed between the active device array layer and the opposite substrate. Moreover, a fabricating method of the touch display panel is also provided.

Abstract: The present invention provides a battery module state detection method. The battery module includes a battery unit and is connected to a load. The method for detecting the battery module status includes the following steps. First, measure an on-load voltage value of the battery unit and a load current value of a load. Next, calculate an instant resistance value of the battery unit according to a no-load voltage value of the battery unit, the on-load voltage value and the load current value. Finally, obtain an operating state of the battery unit according to the instant resistance and a relationship between the internal resistance and discharging time. By the method of the present invention, the user can monitor the remaining energy of the battery module accurately in real time and therefore prevent the electrical hazard caused by over-discharging the battery module.