Patents by Inventor Chin-Chun Huang
Chin-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210242129Abstract: A method for fabricating semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate, patterning the first IMD layer to form first IMD patterns on the substrate, a trench surrounding the first IMD patterns, and a second IMD pattern surrounding the trench, forming a metal layer in the trench to surround the first IMD patterns, forming a second IMD layer on the first IMD patterns, the metal layer, and the second IMD pattern, and forming via conductors in the second IMD layer. Preferably, the via conductors not overlapping the first IMD patterns.Type: ApplicationFiled: April 9, 2020Publication date: August 5, 2021Inventors: BIN GUO, Hailong Gu, Chin-Chun Huang, Wen Yi Tan
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Publication number: 20210202578Abstract: An RRAM structure includes a substrate. An RRAM is embedded in the substrate. The RRAM includes a bottom electrode, a metal oxide layer and a top electrode. A first doped region is embedded in the substrate and surrounds the bottom electrode. A transistor is disposed on the substrate and at one side of the RRAM. The transistor includes a gate structure on the substrate. A source is disposed in the substrate and at one side of the gate structure. A drain is disposed in the substrate and at another side of the gate structure. The first doped region contacts the drain.Type: ApplicationFiled: January 13, 2020Publication date: July 1, 2021Inventors: Chin-Chun Huang, Yun-Pin Teng, JINJIAN OUYANG, WEN YI TAN
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Patent number: 11049904Abstract: An RRAM structure includes a substrate. An RRAM is embedded in the substrate. The RRAM includes a bottom electrode, a metal oxide layer and a top electrode. A first doped region is embedded in the substrate and surrounds the bottom electrode. A transistor is disposed on the substrate and at one side of the RRAM. The transistor includes a gate structure on the substrate. A source is disposed in the substrate and at one side of the gate structure. A drain is disposed in the substrate and at another side of the gate structure. The first doped region contacts the drain.Type: GrantFiled: January 13, 2020Date of Patent: June 29, 2021Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Chin-Chun Huang, Yun-Pin Teng, Jinjian Ouyang, Wen Yi Tan
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Patent number: 10937830Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.Type: GrantFiled: May 6, 2020Date of Patent: March 2, 2021Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Chin-Chun Huang, Yun-Pin Teng, You-Di Jhang, Wen Yi Tan
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Publication number: 20200266237Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.Type: ApplicationFiled: May 6, 2020Publication date: August 20, 2020Inventors: Chin-Chun Huang, Yun-Pin Teng, You-Di Jhang, WEN YI TAN
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Patent number: 10692929Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.Type: GrantFiled: December 24, 2018Date of Patent: June 23, 2020Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Chin-Chun Huang, Yun-Pin Teng, You-Di Jhang, Wen Yi Tan
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Publication number: 20200185456Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.Type: ApplicationFiled: December 24, 2018Publication date: June 11, 2020Inventors: Chin-Chun Huang, Yun-Pin Teng, You-Di Jhang, WEN YI TAN
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Patent number: 9664227Abstract: A vacuum retaining device capable of reuse includes a sucking disk member. The periphery of a disk surface portion of the sucking disk member is formed with a coupling edge portion wrapped and connected with a sealing rim. During use, the coupling edge portion inside the sealing rim forms a support, such that the shape and efficiency of the sealing rim can be kept for a long time. When a sealing surface of the sealing rim is poked to disengage from a surface to be adhered, the sealing surface is able to link the coupling edge portion of the sucking disk body. When the vacuum retaining device is not used, the outer edge of the sealing rim is poked for the air to enter the interior of the sucking disk body. The vacuum retaining device can be detached from the surface easily and conveniently.Type: GrantFiled: April 4, 2016Date of Patent: May 30, 2017Assignee: Canshow Industrial Co., Ltd.Inventors: Jin-Shu Huang, Jin-Dian Huang, Chin-Chun Huang, Chinhung Huang, Lien-Yung Huang
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Publication number: 20160215813Abstract: A vacuum retaining device capable of reuse includes a sucking disk member. The periphery of a disk surface portion of the sucking disk member is formed with a coupling edge portion wrapped and connected with a sealing rim. During use, the coupling edge portion inside the sealing rim forms a support, such that the shape and efficiency of the sealing rim can be kept for a long time. When a sealing surface of the sealing rim is poked to disengage from a surface to be adhered, the sealing surface is able to link the coupling edge portion of the sucking disk body. When the vacuum retaining device is not used, the outer edge of the sealing rim is poked for the air to enter the interior of the sucking disk body. The vacuum retaining device can be detached from the surface easily and conveniently.Type: ApplicationFiled: April 4, 2016Publication date: July 28, 2016Inventors: Jin-Shu Huang, Jin-Dian Huang, Chin-Chun Huang, Chinhung Huang, Lien-Yung Huang
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Publication number: 20160133559Abstract: A semiconductor structure includes a substrate comprising a plurality of layers formed thereon, at least a first device formed in one of the layers formed thereon, a drawn region enclosing the first device, and a plurality of dummy structures in another layer. The dummy structures are formed in a first region correspondingly outside of the drawing region and in a second region correspondingly inside of the drawing region.Type: ApplicationFiled: November 11, 2014Publication date: May 12, 2016Inventors: Jui-Fa Lu, Chin-Chun Huang, Chun-Nien Chen
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Patent number: 9024407Abstract: A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.Type: GrantFiled: December 7, 2011Date of Patent: May 5, 2015Assignee: United Microelectronics CorporationInventors: Chin-Chun Huang, Ji-Fu Kung, Wei-Po Chiu, Nick Chao
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Publication number: 20130147510Abstract: A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chin-Chun HUANG, Ji-Fu Kung, Wei-Po Chiu, Nick Chao
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Patent number: 8441445Abstract: An electrophoretic display keypad structure utilizes a whole piece of electrophoretic display film to show a plurality of figures for keys. The electrophoretic display film is disposed on a printed circuit board having a patterned electrode and sealed by a sealant or a sealing material applied to entire periphery of the electrophoretic display film for preventing humidity or pollution, thereby to display excellent figures and be made relatively easily. The figures displayed may be changed by selecting a desired mode, and users may accordingly easily choose desired figures for pressing the keys.Type: GrantFiled: April 16, 2010Date of Patent: May 14, 2013Assignee: Ichia Technologies, Inc.Inventor: Chin-Chun Huang
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Publication number: 20120301630Abstract: A method for forming a flexible printed circuit board is provided. First, an insulating substrate with a first side and a second side is provided. Second, a through hole connecting the first side and the second side is formed in the insulating substrate. Then, a printing step is carried out to print a conductive precursor which is on the first side and cover and fill the through hole. Later, the conductive precursor is cured to form a conductive composition and to simultaneously form a circuit to obtain a flexible printed circuit board. The conductive composition includes at least one of carbon and silver.Type: ApplicationFiled: September 22, 2011Publication date: November 29, 2012Inventor: Chin-Chun Huang
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Patent number: 8207872Abstract: A mechanical keypad with touch panel function includes a key set including a plurality of keycaps and a keytop covering the keycaps, a backlight layer under the key set, a capacitive touch unit selectively disposed under several keycaps, an elastic layer including an elastomer and a plunger corresponding to the keycaps and disposed under the capacitive touch unit as well as a circuit board including metal domes and dome sheets corresponding to the keycaps. Each metal dome provides a mechanical feedback force so that the keycaps are able to be in indirect contact with the metal domes and the dome sheets by means of the plunger.Type: GrantFiled: October 11, 2009Date of Patent: June 26, 2012Assignee: Ichia Technologies, Inc.Inventors: Chin-Chun Huang, Yi-Hsiang Hsiao, Shih-Pu Yu
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Publication number: 20110148766Abstract: An electrophoretic display keypad structure utilizes a whole piece of electrophoretic display film to show a plurality of figures for keys. The electrophoretic display film is disposed on a printed circuit board having a patterned electrode and sealed by a sealant or a sealing material applied to entire periphery of the electrophoretic display film for preventing humidity or pollution, thereby to display excellent figures and be made relatively easily. The figures displayed may be changed by selecting a desired mode, and users may accordingly easily choose desired figures for pressing the keys.Type: ApplicationFiled: April 16, 2010Publication date: June 23, 2011Inventor: Chin-Chun Huang
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Publication number: 20100309030Abstract: A mechanical keypad with touch panel function includes a key set including a plurality of keycaps and a keytop covering the keycaps, a backlight layer under the key set, a capacitive touch unit selectively disposed under several keycaps, an elastic layer including an elastomer and a plunger corresponding to the keycaps and disposed under the capacitive touch unit as well as a circuit board including metal domes and dome sheets corresponding to the keycaps. Each metal dome provides a mechanical feedback force so that the keycaps are able to be in indirect contact with the metal domes and the dome sheets by means of the plunger.Type: ApplicationFiled: October 11, 2009Publication date: December 9, 2010Inventors: Chin-Chun Huang, Yi-Hsiang Hsiao, Shih-Pu Yu
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Patent number: 6376359Abstract: A method of manufacturing metallic interconnects capable of reducing internal stress inside the metallic layer. The method comprises the steps of forming a silicon-rich oxide layer both before and after the formation of a metallic layer. Therefore, the metallic layer is fully enclosed by silicon-rich oxide layers and any direct contact between the metallic layer and any silicon dioxide layer is avoided. Since the quantity of silicon in the silicon-rich oxide layer is much higher than in a silicon dioxide layer, bonds formed between a silicon atom and an oxygen atom in the silicon-rich oxide layer are much stronger. Consequently, the chance for an aluminum atom in the metallic layer to react with an oxygen atom in the silicon-rich oxide layer is greatly reduced. Hence, lattice vacancies/voids that can lead to conventional stress migration and thermal induced migration problems are prevented.Type: GrantFiled: May 15, 1998Date of Patent: April 23, 2002Assignee: United Microelectronics Corp.Inventors: Yei-Hsiung Lin, Chen-Bin Lin, Chin-Chun Huang
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Patent number: 6114196Abstract: A method of fabricating a MOS transistor. An undoped multi-layer stacked polysilicon structure is formed on a gate oxide layer and then being doped to increase conductivity. After that, the multi-layer stacked polysilicon structure and the gate oxide layer are patterned to form a gate electrode. A source/drain region is formed by ion implantation with the gate electrode as a mask.Type: GrantFiled: January 11, 1999Date of Patent: September 5, 2000Assignee: United Microelectronics Corp.Inventors: Yei-Hsiung Lin, Chen-Bin Lin, Yu-Ju Liu, Chin-Chun Huang
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Patent number: 5540130Abstract: A saw machine includes a base body with rear and front portions. A worktable extends from the rear portion toward the front portion, and has a sawing slot formed therethrough. An upright support arm has an intermediate section pivoted to the rear portion of the base body. An upper hollow arm extends above the front portion of the base body from an upper section of the support arm. A lower hollow arm extends below the front portion of the base body from a lower section of the support arm. A pair of upper and lower levers have rear ends pivoted respectively in the upper and lower hollow arms, and front ends aligned with each other to define cooperatively a straight line that passes through the sawing slot. An elongated saw blade has two ends connected to the front ends of the upper and lower levers so as to pass through the sawing slot.Type: GrantFiled: September 27, 1994Date of Patent: July 30, 1996Assignee: Chin-Chun HuangInventors: Chin-Chun Huang, Hsiu-Tzu Lin