Abstract: An apparatus may include a heat pipe with a first portion residing in a first plane, a second portion residing in the first plane and a third portion positioned between the first portion and the second portion, the third portion residing in a second plane spaced-apart from the first plane. The apparatus further includes a base plate including an opening and a clip plate having a first region, a second region and a third region positioned between the first and the second regions. The third portion of the heat pipe is positioned within the opening, and the clip plate is coupled to the base plate such that i) the third region of the clip plate is in superimposition with the third portion of the heat pipe and ii) third region of the clip plate resides in the first plane.

Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: A method for manufacturing an operation rod of a wrench assembly for disassembling a fan clutch, including following steps of: preparing a rod material; fixing the rod material on a forging mold; carrying out a forging process to produce a semi-finished head; carrying out a cutout process, cutting the remainder structure out of the semi-finished head; obtaining a finished product of a head portion, the head portion including two wing plates and a shaft which are integrally formed.

Abstract: A method for manufacturing an operation rod of a wrench assembly for disassembling a fan clutch, including following steps of: preparing a rod material; fixing the rod material on a forging mold; carrying out a forging process to produce a semi-finished head; carrying out a cutout process, cutting the remainder structure out of the semi-finished head; obtaining a finished product of a head portion, the head portion including two wing plates and a shaft which are integrally formed.

Abstract: A fan clutch wrench is provided, including a rod and a driving member. The driving member includes a longitudinal direction and a thickness direction, two opposite ends of the driving member on the longitudinal direction are respectively defined as a first end and a second end, the second end is rotatably connected to the rod, an engagement hole penetrates through the first end in the thickness direction, the engagement hole penetrates through the first end to form a first lateral opening along a direction which is lateral to the thickness direction and lateral to the longitudinal direction, and the first lateral opening is for a fastener of a fan clutch to pass therethrough to be engaged with the engagement hole.

Abstract: An organic electroluminescent device with improved lifetime and a method of fabricating the same are provided. The device comprises a barrier layer on an upper surface of a color filter, and etching and removing part of the barrier layer uncovered by first electrodes to form moistness removed channel after defining and forming at least one first electrode on an upper surface of the barrier layer. It is convenient to bake and eliminate a solvent or mist existed in the color filter in a baking process, thereby reducing speed of going bad of the organic light emitting layer and effectively improving lifetime of the organic electroluminescent device.

Abstract: An electrode structure of an organic electroluminescent display panel and a method of manufacturing the same are provided. The electrode structure comprises a transparency substrate, a leading wire pattern layer (for example: ITO, IZO or IWO materials etc.) grown on the transparency substrate, at least one auxiliary metallic pattern layer grown on the leading wire pattern layer, an isolation area provided on the auxiliary metallic pattern layer for isolation, a separation area provided on the isolation area with an raised predetermined height to separate electric interference, and at least one metallic conductive layer provided on the transparency substrate and the separation area.

Abstract: A connecting circuit structure is provided for a circuit carrier. The circuit connecting structure includes at least two insulating layers, two conductive layers, and one conductive pad, wherein a via hole is formed from each of the insulating layers through corresponding insulating layer. One insulating layer is formed over the other. The conductive pad is disposed between the two insulating layers, and two surfaces of the conductive pad are connected to the two via holes respectively. Two conductive layers are respectively formed in the via hole on a same side of the circuit connecting structure in order to connect to the conductive pad respectively. Since a depth/width ratio of the via hole is reduced according to the circuit connecting structure in the present invention, voids and bubbles are effectively avoided and the reliability of fabricating method thereof is increased.

Abstract: A method of forming a micro-via, for fabrication and design of a layout of a circuit board. A patterned conductive wiring layer is formed on the substrate. A copper layer is plated onto the substrate and the conductive wiring layer. A photoresist layer is formed on the copper layer. A part of the photoresist layer is removed to expose a part of the copper layer. Using the copper layer as a seed layer, a conductive pillar is formed on the exposed part of the copper layer. The photoresist layer is removed. The exposed plated copper layer is removed. An insulation layer is formed on surfaces of the substrate and the conductive pillar. A part of the insulation layer is removed to expose the conductive pillar. A patterned conductive wiring layer is formed on the conductive pillar.