Abstract: A method for estimating a risk for a subject suffering from encapsulating peritoneal sclerosis is provided, including measuring an expression level of at least one microRNA from a sample of the subject, and the microRNA is selected from miR-17, miR-100, miR-155, miR-202, miR-422a, and miR-483; comparing the expression level of the microRNA in the sample to that of a same miRNA of a control, when the expression level of miRNA in the sample is lower than that of the control, the subject is estimated having the risk of encapsulating peritoneal sclerosis. A kit for estimating a risk for a subject suffering from encapsulating peritoneal sclerosis is also provided, including at least one agent for identifying the at least one microRNA as above mentioned from the sample of the subject.

Abstract: A method for estimating a risk for a subject suffering from encapsulating peritoneal sclerosis is provided, including measuring an expression level of at least one microRNA from a sample of the subject, and the microRNA is selected from miR-17, miR-100, miR-155, miR-202, miR-422a, and miR-483; comparing the expression level of the microRNA in the sample to that of a same miRNA of a control, when the expression level of miRNA in the sample is lower than that of the control, the subject is estimated having the risk of encapsulating peritoneal sclerosis. A kit for estimating a risk for a subject suffering from encapsulating peritoneal sclerosis is also provided, including at least one agent for identifying the at least one microRNA as above mentioned from the sample of the subject.

Abstract: A testing system is described for testing a memory device. The testing system includes a timing generator, an optional frequency multiplier circuit, a pattern generator, and a waveform shaping circuit. The timing generator generates a first clock signal. The frequency multiplier circuit receives the first clock signal, and uses the first clock signal to produce a second clock signal. In general, the second clock signal has a frequency greater than a frequency of the first clock signal. The frequency of the second clock signal may twice the frequency of the first clock signal. The testing system provides the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal. The waveform shaping circuit produces an address signal synchronized to the first clock signal, and provides the address signal to the memory device when reading data from the memory device.

Abstract: A testing system is described for testing a memory device. The testing system includes a timing generator, an optional frequency multiplier circuit, a pattern generator, and a waveform shaping circuit. The timing generator generates a first clock signal. The frequency multiplier circuit receives the first clock signal, and uses the first clock signal to produce a second clock signal. In general, the second clock signal has a frequency greater than a frequency of the first clock signal. The frequency of the second clock signal may twice the frequency of the first clock signal. The testing system provides the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal. The waveform shaping circuit produces an address signal synchronized to the first clock signal, and provides the address signal to the memory device when reading data from the memory device.