Patents by Inventor Chin-Fa Hsiao
Chin-Fa Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8687681Abstract: A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same.Type: GrantFiled: April 11, 2013Date of Patent: April 1, 2014Assignee: VIA Technologies, Inc.Inventors: Chin-Fa Hsiao, Shih-Min Lin
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Publication number: 20130230132Abstract: A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same.Type: ApplicationFiled: April 11, 2013Publication date: September 5, 2013Applicant: Via Technologies, Inc.Inventors: Chin-Fa Hsiao, Shih-Min Lin
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Patent number: 8014440Abstract: A frequency adjusting method of a CDR circuit and apparatus thereof are provided. The adjusting method is applied to a receiver apparatus connected to an outer apparatus. The outer apparatus, after actuated, sends out an outer data signal to the receiver apparatus according to its operational frequency and a PLL of the receiver apparatus outputs a transmitter clock according to an operational frequency of the receiver apparatus. The CDR circuit of the receiver apparatus generates a receiver clock according to the outer data signal. The CDR circuit is set in a phase mode such that the receiver clock follows transmitting frequency of the outer data signal. Then, a difference between frequencies of the receiver clock and the transmitter clock is checked. If the difference is larger than a threshold value, an operational frequency of the outer data signal is reduced.Type: GrantFiled: March 2, 2007Date of Patent: September 6, 2011Assignee: VIA Technologies, Inc.Inventor: Chin-Fa Hsiao
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Patent number: 7900028Abstract: In a method used for initializing a first bus device and a second bus device sharing a common transmission engine of a bus, a first link of the first bus device and a second link of the second bus device to the common transmission engine are disabled when the computer system is booted. Next, the first link and the second link are enabled in order. Then, a first state updating signal from the first bus device is issued after the first link to the common transmission engine is established. Finally, a second state updating signal from the second bus device is issued after the first state updating signal is received and the second link to the common transmission engine is established.Type: GrantFiled: October 4, 2006Date of Patent: March 1, 2011Assignee: Via Technologies, Inc.Inventors: Chung-Ching Huang, Ta-Chuan Liu, Tzu-Chiang Chiu, Chin-Fa Hsiao
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Publication number: 20080056339Abstract: A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same.Type: ApplicationFiled: June 28, 2007Publication date: March 6, 2008Applicant: VIA Technologies, Inc.Inventors: Chin-Fa Hsiao, Shih-Min Lin
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Publication number: 20080043892Abstract: A frequency adjusting method of a CDR circuit and apparatus thereof are provided. The adjusting method is applied to a receiver apparatus connected to an outer apparatus. The outer apparatus, after actuated, sends out an outer data signal to the receiver apparatus according to its operational frequency and a PLL of the receiver apparatus outputs a transmitter clock according to an operational frequency of the receiver apparatus. The CDR circuit of the receiver apparatus generates a receiver clock according to the outer data signal. The CDR circuit is set in a phase mode such that the receiver clock follows transmitting frequency of the outer data signal. Then, a difference between frequencies of the receiver clock and the transmitter clock is checked. If the difference is larger than a threshold value, an operational frequency of the outer data signal is reduced.Type: ApplicationFiled: March 2, 2007Publication date: February 21, 2008Applicant: VIA Technologies, Inc.Inventor: Chin-Fa Hsiao
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Publication number: 20070088879Abstract: In a method used for initializing a first bus device and a second bus device sharing a common transmission engine of a bus, a first link of the first bus device and a second link of the second bus device to the common transmission engine are disabled when the computer system is booted. Next, the first link and the second link are enabled in order. Then, a first state updating signal from the first bus device is issued after the first link to the common transmission engine is established. Finally, a second state updating signal from the second bus device is issued after the first state updating signal is received and the second link to the common transmission engine is established.Type: ApplicationFiled: October 4, 2006Publication date: April 19, 2007Applicant: VIA TECHNOLOGIES, INC.Inventors: Chung-Ching Huang, Ta-Chuan Liu, Tzu-Chiang Chiu, Chin-Fa Hsiao
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Patent number: 7049839Abstract: A chip capable of performing self testing includes: an output circuit for generating output signals; a transmitting circuit coupled to the output circuit for transmitting output signals generated by the output circuit; a receiving circuit for receiving signals transmitted to the chip and generating corresponding receiving signals; a first multiplexer; and an input circuit coupled to an output port of the first multiplexer for receiving outputs of the first multiplexer, wherein the first multiplexer includes: a first input port coupled to the output circuit for receiving output signals generated by the output circuit; and a second input port coupled to the receiving circuit for receiving signals generated by the receiving circuit.Type: GrantFiled: June 30, 2005Date of Patent: May 23, 2006Assignee: VIA Technologies Inc.Inventors: Chin-Fa Hsiao, Chin-Yi Chiang
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Patent number: 6966041Abstract: The present invention discloses a chip fabrication procedure as well as a simulation method for chip testing with performance pre-testing. The chip fabrication procedure with performance pre-testing comprising steps of: providing a chip design; determining if the chip design is correct by using a simulation environment; determining if the chip performance meets the standards by using a performance testing process; and proceeding with production of chips. The simulation method for chip testing comprises steps of: providing a simulation environment corresponding to a chip design; providing at least one set of testing commands; executing the testing commands; and calculating the time required for completing executing the testing commands. The present invention is advantageous since the time requited for product testing is reduced and so is the fabrication cost.Type: GrantFiled: August 12, 2002Date of Patent: November 15, 2005Assignee: Via Technologies, Inc.Inventors: FuChu Wen, Tony Han, Chin-Fa Hsiao
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Publication number: 20030208722Abstract: The present invention discloses a chip fabrication procedure as well as a simulation method for chip testing with performance pre-testing. The chip fabrication procedure with performance pre-testing comprising steps of: providing a chip design; determining if the chip design is correct by using a simulation environment; determining if the chip performance meets the standards by using a performance testing process; and proceeding with production of chips. The simulation method for chip testing comprises steps of: providing a simulation environment corresponding to a chip design; providing at least one set of testing commands; executing the testing commands; and calculating the time required for completing executing the testing commands. The present invention is advantageous since the time requited for product testing is reduced and so is the fabrication cost.Type: ApplicationFiled: August 12, 2002Publication date: November 6, 2003Inventors: Fuchu Wen, Tony Han, Chin-Fa Hsiao