Abstract: An image capture device capable of uploading clear images via wireless transmission includes a central processing unit, an image capture unit electrically coupled to the central processing unit, an image memory unit, a clear image detection unit electrically coupled to the central processing unit, and a wireless transmission unit electrically coupled to the central processing unit and these units are operated together to upload clear images, particularly to upload clear images to an external storage device via wireless transmission.

Abstract: A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities.

Abstract: An inner-connecting structure of a lead frame. The lead frame includes a metal frame having a plurality of leads. The inner-connecting structure of the lead frame includes an insulation film arranged on some of those leads, covering a portion of a first surface of the lead; a plurality of holes formed on the insulation film to expose some of those leads, wherein the hole exposes a portion of the first surface of the lead; and a conductive element selectively connecting the exposed portion of those leads electrically. Besides, an inner-connecting method of the lead frame is also disclosed herein. The insulation film is utilized to separate the conductive element from the lead frame so that the leads can be easily interconnected with each other.

Abstract: A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities.

Abstract: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code.

Abstract: A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed on a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane and the second plane. The internal tie bar has at least two or more windings such as “S” shaped to flexibly connect the baffle paddle to an adjacent one of the leads. Therefore, the internal tie bar can reduce the shifting and twisting of the connected lead during the formation of the downset of the baffle paddle.

Abstract: An inner-connecting structure of the lead frame is disclosed in the present invention, which includes a plurality of leads, an insulation film arranged on a portion of a first surface of those leads, a plurality of holes formed on the insulation film to expose a portion of the first surface of a portion of those leads, and a conductive element selectively connecting the exposed portion of those leads electrically. Besides, an inner-connecting method of the lead frame is also disclosed herein. The insulation film is utilized to separate the conductive element from the lead frame so that the lead can be easily interconnected with each other.

Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die- bonding plane under the chip is desirably prevented.

Abstract: A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die-bonding plane under the chip is desirably prevented.

Abstract: A chip mounting device includes at least one chip mounting unit and at least one side rail configured beside the chip mounting unit. The chip mounting unit includes a die pad and a plurality of conductive contacts. The side rail includes at least one identifying element. A chip package array with the above-mentioned chip mounting device is also disclosed. The chip mounting device and chip package array includes the identifying element configured on the side rail to improve the identification of semi-finished packaged chips during chip package process to be read automatically by machines instead of operators, and further decrease the loss caused by misjudgments of operators.

Abstract: A Chip-On-Lead (COL) semiconductor package is revealed, primarily comprising a plurality of leadframe's leads each having a carrying bar, a finger and a connecting portion connecting the carrying bar to the finger. A chip has a back surface attached to the carrying bars and is electrically connected to the fingers by a plurality of bonding wires. Therein, at least one of the bonding wires overpasses one of the connecting portions without electrical relationship. An insulation tape is attached onto the connecting portions in a manner to be formed between the overpassing section of the bonding wire and the overpast connecting portion so that electrical short can be avoided during wire-bonding processes of the COL semiconductor package. Therefore, the carrying bars under the chip have more flexibility in the layout design of COL semiconductor packages to use die pad(s) with smaller dimensions or even eliminate die pad.

Abstract: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code.

Abstract: A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed oil a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane and the second plane. The internal tie bar has at least two or more windings such as “S” shaped to flexibly connect the baffle paddle to an adjacent one of the leads. Therefore, the internal tie bar can reduce the shifting and twisting of the connected lead during the formation of the downset of the baffle paddle.

Abstract: A semiconductor package primarily comprises a plurality of leadframe's leads, a chip, a paddle, an adhesive and an encapsulant encapsulating the components mentioned above. The paddle has a carrying surface and an exposed external surface. The first chip is attached to one surface of the leads. The paddle is attached to an opposing surface of the leads by the adhesive bonding the carrying surface to the leads. Furthermore, the adhesive further encapsulates the gaps between the leads without contaminating the exposed external surface and with the exposed external surface exposed from the encapsulant. Therefore, the leads obtain a better support so that the encapsulated portions of the leads will not shift nor expose from the encapsulant during molding processes without encapsulated bubbles between the leads and the paddle. The heat dissipation is also enhanced.

Abstract: A method of forming an identification code for wire bonders is revealed. Firstly, a chip with a plurality of bonding pads is provided and is disposed on a chip carrier with a plurality of bonding fingers. A binary-code baseline is defined on the chip carrier to divide each of the bonding fingers into a first coding area adjacent the bonding pads and a second coding area far away from the bonding pads. Then, a plurality of bonding wires are formed by wire bonding to electrically connect the bonding pads to the bonding fingers and an ID code for wire bonders is formed at the same time where each bonding wire has an end selectively bonded to either the first coding area or the second coding area of the corresponding bonding finger to form an ID code for wire bonders. Since the ID code for wire bonders is constituted by the selected locations of the ends of the bonding wires, the ID code do not get lost or damaged during packaging processes nor contaminate the packages.

Abstract: A rug includes a foam base layer and a top layer which is fixed on a top of the foam base layer. The base layer has a plurality of holes and separation portions which are located between the holes. The top layer is woven by plastic fibers and is a porous top layer. The top layer is conveniently woven by artificial plastic fibers so that different patterns and colors are available. The foam base layer is resilient and the holes are good for ventilation.

Abstract: A rug includes a foam base layer and a top layer which is fixed on a top of the foam base layer. The base layer has a plurality of holes and separation portions which are located between the holes. The top layer is woven by plastic fibers and is a porous top layer. The top layer is conveniently woven by artificial plastic fibers so that different patterns and colors are available. The foam base layer is resilient and the holes are good for ventilation.

Abstract: A bond positioning method for a wire-bonding process and a substrate for the bond positioning method are provided. At least one solder mask mark is formed in a solder mask layer on the substrate, such that during the wire-bonding process, the solder mask mark serves as a reference point for determining deviation of the solder mask layer and performing coordinate compensation according to the deviation so as to re-define positioning of a second bonding point of a bonding wire. This can overcome defects relating to bonding wires such as bending, cracking, or detachment of the bonding wires caused by undesirable contact between the bonding wires and the solder mask layer in the conventional wire-bonding process, thereby improving the production yield of the wire-bonding process, reducing material costs associated with defective products, and reducing the overall fabrication costs.

Abstract: A rope includes two groups of yarn wires which are respectively coated by a coating made of PUC foam plastic. The coatings are arranged in parallel with each other and connected by a connection portion. The coatings can be dyed as different colors. Two or more ropes can be woven together to be a reinforced rope when necessary.

Abstract: A semiconductor package and a fabrication method thereof are provided, in which a ground pad on a chip is electrically connected to a ground plane on a substrate by means of an electrically-conductive wall formed over a side surface of the chip and an electrically-conductive adhesive used for attaching the chip to the substrate. Therefore, a wire-bonding process is merely implemented for power pads and signal I/O (input/output) pads on the chip without having to form ground wires on the ground pads for electrical connection purposes. This benefit allows the use of a reduced number of bonding wires and simplifies wire arrangement or routability. And, a grounding path from the chip through the electrically-conductive wall and electrically-conductive adhesive to the substrate is shorter than the conventional one of using ground wires, thereby reducing a ground-bouncing effect and improving electrical performances of the semiconductor package.