Patents by Inventor Chin-Fong Chiu
Chin-Fong Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8704580Abstract: The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.Type: GrantFiled: August 24, 2012Date of Patent: April 22, 2014Assignee: National Applied Research LaboratoriesInventors: Chin-Fong Chiu, Hann-Huei Tsai, Wen-Hsu Chang, Chih-Cheng Hsieh, Kuo-Wei Cheng
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Publication number: 20130335132Abstract: The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.Type: ApplicationFiled: August 24, 2012Publication date: December 19, 2013Applicant: National Applied Research LaboratoriesInventors: Chin-Fong CHIU, Hann-Huei TSAI, Wen-Hsu CHANG, Chih-Cheng HSIEH, Kuo-Wei CHENG
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Patent number: 8466521Abstract: A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.Type: GrantFiled: March 16, 2010Date of Patent: June 18, 2013Assignee: National Chip Implementation Center National Applied Research LaboratoriesInventors: Chin-Long Wey, Chin-Fong Chiu, Ying-Zong Juang, Hann-Huei Tsai, Chen-Fu Lin
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Patent number: 8451078Abstract: A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.Type: GrantFiled: June 15, 2011Date of Patent: May 28, 2013Assignees: National Chip Implementation Center, National Applied Research LaboratoriesInventors: You-Liang Lai, Ying-Zong Juang, Hann-Huei Tsai, Sheng-Hsiang Tseng, Chin-Fong Chiu
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Patent number: 8410480Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.Type: GrantFiled: February 19, 2010Date of Patent: April 2, 2013Assignee: National Chip Implementation Center National Applied Research LaboratoriesInventors: Chin-Fong Chiu, Ying Zong Juang, Hann Huei Tsai, Sheng-Hsiang Tseng, Chen-Fu Lin
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Publication number: 20120279838Abstract: A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.Type: ApplicationFiled: June 15, 2011Publication date: November 8, 2012Applicant: National Chip Implementation Center National Applied Research Laboratories.Inventors: You-Liang LAI, Ying-Zong JUANG, Hann-Huei TSAI, Sheng-Hsiang TSENG, Chin-Fong CHIU
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Patent number: 8158063Abstract: A biosensor package structure with a micro-fluidic channel is provided. The biosensor package structure includes a substrate, a biochip, and a cover. The substrate has a first surface, a second surface, and an opening. The biochip is attached on the first surface. A bio-sensing area of the biochip is exposed to the opening of the substrate. The cover is attached on the second surface to cover the opening so as to form a micro-fluidic channel. By implementing the invention, the manufacturing process of the biosensor is simplified and the productivity is increased.Type: GrantFiled: December 12, 2008Date of Patent: April 17, 2012Assignee: National Chip Implementation Center National Applied Research LaboratoriesInventors: Chin-Fong Chiu, Ying-Zong Juang, Hann-Huei Tsai, Chen-Fu Lin
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Publication number: 20110169056Abstract: A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.Type: ApplicationFiled: March 16, 2010Publication date: July 14, 2011Applicant: National Chip Implementation Center National Applied Research Laboratories.Inventors: Chin-Long Wey, Chin-Fong Chiu, Ying-Zong Juang, Hann-Huei Tsai, Chen-Fu Lin
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Publication number: 20110133256Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.Type: ApplicationFiled: February 19, 2010Publication date: June 9, 2011Applicant: National Chip Implementation Center National Applied Research LaboratoriesInventors: Chin-Fong Chiu, Ying Zong Juang, Hann Huei Tsai, Sheng-Hsiang Tseng, Chen-Fu Lin
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Publication number: 20110117747Abstract: A method of fabricating a single chip for integrating a field-effect transistor into a microelectromechanical systems (MEMS) structure is provided. The method includes the steps of: providing a substrate having thereon at least one transistor structure, a MEMS structure and a blocking structure, wherein the blocking structure encircles the MEMS structure to separate the MEMS structure from the transistor structure; forming a masking layer for covering the transistor structure, the MEMS structure and the blocking structure; forming a patterned photoresist layer on the masking layer; performing a first etching process by using the patterned photoresist layer to remove the masking layer on the MEMS structure; and performing a second etching process by removing a portion of the MEMS structure to form a plurality of microstructures such that a relative motion among the microstructures takes place in a direction perpendicular to the substrate.Type: ApplicationFiled: January 5, 2010Publication date: May 19, 2011Applicant: National Chip Implementation Center National Applied Research LaboratoriesInventors: Chin-Long Wey, Chin-Fong Chiu, Ying-Zong Juang, Hann-Huei Tsai, Sheng-Hsiang Tseng, Hsin-Hao Liao
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Patent number: 7769360Abstract: An adapter for RF front end processor chip wherein the RF front end processor chip includes a low noise amplifier which is used to receive a RF filter signal so as to generate a first signal. An adapter is used to receive a first signal so as to induce and generate a second signal and a third signal which is electrically reverse. Then a frequency mixer of the RF front end processor chip is used to receive the second signal and the third signal and a resonant signal, the second signal and the third signal are used to generate a medium frequency signal. Wherein, adapter includes a primary measured coil.Type: GrantFiled: February 7, 2007Date of Patent: August 3, 2010Assignee: National Applied Research LaboratoriesInventors: Hsien-Ku Chen, Shey-Shi Lu, Da-Chiang Chang, Ying-Zong Juang, Chin-Fong Chiu
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Publication number: 20100098585Abstract: A biosensor package structure with a micro-fluidic channel is provided. The biosensor package structure includes a substrate, a biochip, and a cover. The substrate has a first surface, a second surface, and an opening. The biochip is attached on the first surface. A bio-sensing area of the biochip is exposed to the opening of the substrate. The cover is attached on the second surface to cover the opening so as to form a micro-fluidic channel. By implementing the invention, the manufacturing process of the biosensor is simplified and the productivity is increased.Type: ApplicationFiled: December 12, 2008Publication date: April 22, 2010Applicant: National Chip Implementation Center National Applied Research LaboratoiesInventors: Chin-Fong CHIU, Ying-Zong Juang, Hann-Huei Tsai, Chen-Fu Lin
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Publication number: 20100099582Abstract: A biochip package structure is provided. The biochip package structure includes a substrate, a biochip, at least one wire, and a molding compound. The substrate has a circuit unit electrically connected, by wiring, to the biochip defined with a sensing region. The molding compound covers the wire but leaves the sensing region of the biochip exposed, allowing a cavity to be formed in the sensing region. The cavity delivers a biomedical sample. The biomedical sample reacts in the sensing region. Thus, the biochip package structure is applicable to various medical and biochemical assays.Type: ApplicationFiled: December 17, 2008Publication date: April 22, 2010Applicant: National Chip Implementation Center National Applied Research LaboratoriesInventors: Chin-Fong Chiu, Ying-Zong Juang, Hann-huei Tsai, Chen-Fu Lin
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Publication number: 20090155948Abstract: A manufacture method for CMOS sensor, which comprise of steps such as: forming protection layer on a substrate having multiple device structural layers, then using first photo-resist layer as mask for etching to form patterned molecular sensing layer, then forming third photo resist layer and etching protection layer and substrate so as to remove partial substrate underneath the sensor structure.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Applicant: National Applied Research LaboratoriesInventors: Chen-Fu Lin, Hann-Huei Tsai, Ying-Zong Juang, Chin-Fong Chiu
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Patent number: 7435663Abstract: Simple but practical methods to dice a CMOS-MEMS multi-project wafer are proposed. On this wafer, micromachined microstructures have been fabricated and released. In a method, a photoresist is spun on the full wafer surface, and this photoresist is thick enough to cover all cavities and structures on the wafer, such that the photoresist will protect the released structures free from the chipping, vibrations, and damages in the diamond blade dicing process. In another method, a laser dicing system is utilized to scribe the multi-project wafer placed on a platform, and by precisely controlling the platform moving-track, the dicing path can be programmed to any required shape and region, even it is not straight. In addition, the wafer backside is mounted on a blue-tape at the beginning to enhance the process reliability.Type: GrantFiled: November 10, 2005Date of Patent: October 14, 2008Assignee: National Applied Research Laboratories National Chip International CenterInventors: Sheng-Hsiang Tseng, Fu-Yuan Xiao, Ying-Zong Juang, Chin-Fong Chiu
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Patent number: 7435612Abstract: A fully CMOS compatible MEMS multi-project wafer process comprises coating a layer of thick photoresist on a wafer surface, patterning the photoresist to define a micromachining region, and performing a micromachining in the micromachining region to form suspended microstructures.Type: GrantFiled: November 10, 2005Date of Patent: October 14, 2008Assignee: National Applied Research Laboratories National Chip Implementation CenterInventors: Fu-Yuan Xiao, Ying-Zong Juang, Chin-Fong Chiu
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Publication number: 20080188196Abstract: An adapter for RF front end processor chip wherein the RF front end processor chip includes a low noise amplifier which is used to receive a RF filter signal so as to generate a first signal. An adapter is used to receive a first signal so as to induce and generate a second signal and a third signal which is electrically reverse. Then a frequency mixer of the RF front end processor chip is used to receive the second signal and the third signal and a resonant signal, the second signal and the third signal are used to generate a medium frequency signal.Type: ApplicationFiled: February 7, 2007Publication date: August 7, 2008Inventors: Hsien-Ku Chen, Shey-Shi Lu, Da-Chiang Chang, Ying-Zong Juang, Chin-Fong Chiu
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Publication number: 20060105545Abstract: Simple but practical methods to dice a CMOS-MEMS multi-project wafer are proposed. On this wafer, micromachined microstructures have been fabricated and released. In a method, a photoresist is spun on the full wafer surface, and this photoresist is thick enough to cover all cavities and structures on the wafer, such that the photoresist will protect the released structures free from the chipping, vibrations, and damages in the diamond blade dicing process. In another method, a laser dicing system is utilized to scribe the multi-project wafer placed on a platform, and by precisely controlling the platform moving-track, the dicing path can be programmed to any required shape and region, even it is not straight. In addition, the wafer backside is mounted on a blue-tape at the beginning to enhance the process reliability.Type: ApplicationFiled: November 10, 2005Publication date: May 18, 2006Inventors: Sheng-Hsiang Tseng, Fu-Yuan Xiao, Ying-Zong Juang, Chin-Fong Chiu
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Publication number: 20060105543Abstract: A fully CMOS compatible MEMS multi-project wafer process comprises coating a layer of thick photoresist on a wafer surface, patterning the photoresist to define a micromachining region, and performing a micromachining in the micromachining region to form suspended microstructures.Type: ApplicationFiled: November 10, 2005Publication date: May 18, 2006Inventors: Fu-Yuan Xiao, Ying-Zong Juang, Chin-Fong Chiu
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Patent number: 6825749Abstract: In a symmetric crossover structure of two lines formed of a lower conductor layer and a higher conductor layer above a substrate, each of the two lines is branched to two routes at where they are crossed over to each other. The first route of the first line uses the higher layer to cross the first route of the second line and the lower layer to cross over the second route of the second line. The second route of the first line uses the lower layer to cross over the first route of the second line and the higher layer to cross over the second route of the second line. The two lines therefore have symmetric coupling effects to the substrate.Type: GrantFiled: January 26, 2004Date of Patent: November 30, 2004Assignee: National Applied Research Laboratories National Chip Implementation CenterInventors: Tser Yu Lin, Chin-Fong Chiu, Ying-Zong Juang, Chu-Jung Sha, Li-E Li