Patents by Inventor Chin-Fu Kao
Chin-Fu Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220157692Abstract: A package structure includes a semiconductor package, a thermal conductive gel, a thermal conductive film and a heat spreader. The thermal conductive gel is disposed over the semiconductor package. The thermal conductive film is disposed over the semiconductor package and the thermal conductive gel. A thermal conductivity of the thermal conductive film is different from a thermal conductivity of the thermal conductive gel. The thermal conductive film is surrounded by the heat spreader.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu Wang, Chin-Fu Kao, Szu-Wei Lu
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Publication number: 20220148940Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.Type: ApplicationFiled: January 28, 2022Publication date: May 12, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Publication number: 20220139802Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.Type: ApplicationFiled: January 21, 2022Publication date: May 5, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
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Patent number: 11302683Abstract: A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure.Type: GrantFiled: April 1, 2020Date of Patent: April 12, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11296051Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.Type: GrantFiled: August 22, 2019Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11289399Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a semiconductor package, a thermal conductive gel, a thermal conductive film, and a heat spreader. The semiconductor package has an uneven top surface. The thermal conductive gel covers the uneven top surface of the semiconductor package. The thermal conductive film is over the uneven top surface of the semiconductor package. A thermal conductivity of the thermal conductive film is higher than a thermal conductivity of the thermal conductive gel. The heat spreader is disposed over the thermal conductive film.Type: GrantFiled: February 13, 2020Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu Wang, Chin-Fu Kao, Szu-Wei Lu
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Publication number: 20220037229Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM.Type: ApplicationFiled: July 28, 2020Publication date: February 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
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Patent number: 11239136Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM.Type: GrantFiled: July 28, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
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Patent number: 11239134Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.Type: GrantFiled: January 17, 2020Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11205612Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.Type: GrantFiled: December 9, 2019Date of Patent: December 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
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Publication number: 20210343611Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Inventors: Chih-Hao CHEN, Chih-Chien PAN, Li-Hui CHENG, Chin-Fu KAO, Szu-Wei LU
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Publication number: 20210320097Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20210313304Abstract: A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11121051Abstract: Semiconductor packages and methods of forming the same are disclosed. a semiconductor package includes a die and an underfill. The die is disposed over a surface and includes a first sidewall. The underfill encapsulates the die. The underfill includes a first underfill fillet on the first sidewall, and in a cross-sectional view, a second sidewall of the first underfill fillet has a turning point.Type: GrantFiled: October 16, 2019Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu, Chih-Chien Pan
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Publication number: 20210280519Abstract: A package structure includes a semiconductor die, a plurality of conductive features, a bridge structure, an underfill, via structures and an encapsulant. The conductive features are electrically connected to the semiconductor die, wherein the conductive features include a first group with planar top surfaces, and a second group with uneven top surfaces. The bridge structure is partially overlapped with the semiconductor die and electrically connected to the first group of the conductive feature. The underfill is covering and contacting the first group of the conductive features. The via structures are disposed on and overlapped with the semiconductor die and electrically connected to the second group of the conductive features. The encapsulant is covering and contacting the via structures and the second group of the conductive features.Type: ApplicationFiled: May 10, 2021Publication date: September 9, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hua Chang, Chin-Fu Kao
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Patent number: 11101260Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.Type: GrantFiled: August 1, 2018Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 11101252Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2<H1. The insulating encapsulant is encapsulating the semiconductor die and the plurality of through insulator vias, wherein the insulating encapsulant has a plurality of via openings revealing each of the through insulator vias. The plurality of conductive terminals is disposed in the via openings and electrically connected to the plurality of through insulator vias. The redistribution layer is disposed on the active surface of the semiconductor die and over the insulating encapsulant. The second package is stacked on the first package and electrically connected to the plurality of conductive terminals of the first package.Type: GrantFiled: August 22, 2019Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Lin, Chin-Fu Kao, Jing-Cheng Lin, Li-Hui Cheng, Szu-Wei Lu
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Publication number: 20210249343Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.Type: ApplicationFiled: April 29, 2021Publication date: August 12, 2021Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
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Publication number: 20210225727Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11062968Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed.Type: GrantFiled: August 22, 2019Date of Patent: July 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Chen, Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu