Abstract: Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.

Abstract: Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.

Abstract: Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.

Abstract: An integrated circuit device has first and memory that use first and second normal mode clocks with differing clock domains. A first switching circuit selectively outputs to the first memory the first normal mode clock when the normal mode is selected or the initial test clock as a first test clock when a testing mode is selected, and a second switching circuit selectively outputs to the second memory the second normal mode clock when the normal mode is selected or the test clock as a second test clock when the testing mode is selected. A built-in-self-test switching circuit receives and outputs the first test clock when the first memory is being tested or the second test clock when the second memory is being tested, and a built-in-self-test circuit receives and uses the first test clock for testing the first memory or the second test clock for testing the second memory.

Abstract: An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.

Abstract: Scan chain circuitry is provided for performing scan chain testing of integrated circuits. The integrated circuits being tested may include programmable logic. The scan chain circuitry may include scan chain cells. Each scan chain cell may have a first logic circuit that receives a scan enable signal. When the scan enable signal is asserted, the scan chain cells may be connected to form a scan chain for test data loading and unloading. Each scan chain cell may also include a second logic circuit. The second logic circuit in each scan chain cell may receive a test enable signal. Signal transitions may be created at the output of scan chain cells by loading the scan chain cells with data, deasserting the scan enable signal while the test enable signal is asserted, and applying a clock. At speed delay fault tests may be performed using the scan chain circuitry.

Abstract: An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.