Patents by Inventor Chin Hao Chang
Chin Hao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230408562Abstract: A method and a system for detecting an application program version with abnormal power consumption are provided. The method includes the following. A power consumption database of multiple versions of a target application is established. Power consumption information of a target version of the target application is obtained. According to the power consumption database and the power consumption information, whether the target version of the target application has a first abnormal power consumption state evaluated based on different versions of the target application is determined. In response to the first abnormal power consumption state, an abnormal power consumption prompt corresponding to the target version is generated.Type: ApplicationFiled: November 8, 2022Publication date: December 21, 2023Applicant: ASUSTeK COMPUTER INC.Inventors: Chin-Hao Chang, Shih-Chieh Liao, Tzu-Hung Chuang, Shih-Chuan Chiu, Yi-Nan Lee
-
Publication number: 20230375611Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj Mhala, Calvin Yi-Ping Chao
-
Patent number: 11754616Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.Type: GrantFiled: May 27, 2020Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj M. Mhala, Calvin Yi-Ping Chao
-
Publication number: 20230011763Abstract: The present application provides a gesture determining method and an electronic device. The gesture determining method includes: sensing a control gesture through at least one motion sensor, and correspondingly generating sensing data; sequentially segmenting the sensing data into a plurality of streaming windows according to a unit of time, each streaming window including a group of sensing values; determining whether a sensing value in a streaming window is greater than a critical value, and triggering subsequent gesture recognition when the sensing value is greater than the critical value; and performing a recognition operation on the streaming window by using a gesture recognition model to consecutively output a recognition result; and determining whether the recognition result meets an output condition, and outputting a predicted gesture corresponding to the recognition result when the recognition result meets the output condition.Type: ApplicationFiled: June 20, 2022Publication date: January 12, 2023Inventors: Shih-Chieh Liao, Chin-Hao Chang, Shih-Chuan Chiu, Yi-Nan Lee, Chia-Hao Kang, Wei-Cheng Chen, Tzu-Hung Chuang
-
Publication number: 20220337206Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
-
Patent number: 11424726Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.Type: GrantFiled: April 1, 2020Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
-
Publication number: 20210373068Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.Type: ApplicationFiled: May 27, 2020Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj M. Mhala, Calvin Yi-Ping Chao
-
Publication number: 20210313940Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
-
Patent number: 11131894Abstract: A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N?3, Ma?2, Ma+Mb?N?1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is ?R, and 0<|?R|?10%.Type: GrantFiled: June 29, 2020Date of Patent: September 28, 2021Assignee: Au Optronics CorporationInventors: Chin-Hao Chang, Wei-Li Lin
-
Publication number: 20210173272Abstract: A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N?3, Ma?2, Ma+Mb?N?1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is ?R, and 0<|?R|?10%.Type: ApplicationFiled: June 29, 2020Publication date: June 10, 2021Applicant: Au Optronics CorporationInventors: Chin-Hao Chang, Wei-Li Lin
-
Publication number: 20200030206Abstract: A nail polish composition system includes (a) a base coat nail polish composition including organic solvents, film-forming compounds, plasticizers, and one or more additives; and (b) a top coat nail polish composition including a mixture of cyanoacrylates and a methacrylate. The base coat nail polish composition is applied to a fingernail to form a base coat film. Thereafter, the top coat nail polish composition is applied on or over the base coat film to form a top coat film. The nail polish composition system can significantly shorten the time required for drying the base and top coat nail polish compositions. In addition, the nail polish composition system may be applied without dipping the fingernail in powder glaze.Type: ApplicationFiled: July 24, 2019Publication date: January 30, 2020Inventor: Chin Hao Chang
-
Patent number: 10537509Abstract: A nail glue composition contains Beta-methoxyethyl cyanoacrylate, octyl cyanoacrylate, and polymethyl methacrylate. The nail glue composition is substantially odorless and has increased softness.Type: GrantFiled: April 3, 2018Date of Patent: January 21, 2020Inventor: Chin Hao Chang
-
Publication number: 20190298628Abstract: A nail glue composition contains Beta-methoxyethyl cyanoacrylate, octyl cyanoacrylate, and polymethyl methacrylate. The nail glue composition is substantially odorless and has increased softness.Type: ApplicationFiled: April 3, 2018Publication date: October 3, 2019Inventor: Chin Hao Chang
-
Publication number: 20190281946Abstract: The present invention relates to a lamp for use in curing gel polish applied to nails, such as fingernails or toenails. The lamp includes a housing having an opening for receiving, at least, a part of a hand including one or more fingers or a part of a foot including one or more toes. The lamp also includes one or more retractable feet attached to a bottom of the housing adjacent a front end thereof for elevating the front end of the housing so as to facilitate the insertion or removal, or the proper positioning, of the part of the foot or the hand in or from the opening of the housing. The lamp also includes a bottom plate and a mechanically releasable mechanism for removably attaching the bottom plate to the bottom of the housing.Type: ApplicationFiled: March 14, 2019Publication date: September 19, 2019Inventors: Ryan Kim, Chin Hao Chang
-
Patent number: 10277849Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.Type: GrantFiled: March 30, 2018Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Calvin Yi-Ping Chao, Chin-Hao Chang, Kuo-Yu Chou, Shang-Fu Yeh, Chih-Lin Lee, Chiao-Yi Huang
-
Publication number: 20180227531Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.Type: ApplicationFiled: March 30, 2018Publication date: August 9, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Calvin Yi-Ping Chao, Chin-Hao Chang, Kuo-Yu Chou, Shang-Fu Yeh, Chih-Lin Lee, Chiao-Yi Huang
-
Patent number: 9955096Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.Type: GrantFiled: March 22, 2016Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Calvin Yi-Ping Chao, Shang-Fu Yeh, Chin-Hao Chang, Chih-Lin Lee, Kuo-Yu Chou, Chiao-Yi Huang
-
Publication number: 20170280086Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.Type: ApplicationFiled: March 22, 2016Publication date: September 28, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Calvin Yi-Ping CHAO, Shang-Fu YEH, Chin-Hao CHANG, Chih-Lin LEE, Kuo-Yu CHOU, Chiao-Yi HUANG
-
Patent number: 9543970Abstract: A phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed.Type: GrantFiled: April 17, 2015Date of Patent: January 10, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Min Liu, Chin-Hao Chang
-
Publication number: 20160308541Abstract: A phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: CHIH-MIN LIU, CHIN-HAO CHANG