Patents by Inventor Chin Hao Chang

Chin Hao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186148
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Application
    Filed: February 9, 2024
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Hao CHEN, Wei-Han LAI, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20240155185
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Chia-Hao CHANG, You-Tsai JENG, Kai-Wen YEH, Yi-Cheng CHEN, Te-Chuan WANG, Kai-Wen CHENG, Chin-Lung LIN, Tai-Lai TUNG, Ko-Yin LAI
  • Patent number: 11962847
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 16, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
  • Publication number: 20240113199
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. An interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. The insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.
    Type: Application
    Filed: February 7, 2023
    Publication date: April 4, 2024
    Inventors: Jia-Chuan YOU, Chia-Hao Chang, Kuo-Cheng Chiang, Chin-Hao Wang
  • Patent number: 11935757
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11921164
    Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: March 5, 2024
    Assignee: Dell Products L.P.
    Inventors: Wen-Yung Chang, Chin-Jui Liu, Chien-Hao Chiu
  • Publication number: 20230408562
    Abstract: A method and a system for detecting an application program version with abnormal power consumption are provided. The method includes the following. A power consumption database of multiple versions of a target application is established. Power consumption information of a target version of the target application is obtained. According to the power consumption database and the power consumption information, whether the target version of the target application has a first abnormal power consumption state evaluated based on different versions of the target application is determined. In response to the first abnormal power consumption state, an abnormal power consumption prompt corresponding to the target version is generated.
    Type: Application
    Filed: November 8, 2022
    Publication date: December 21, 2023
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chin-Hao Chang, Shih-Chieh Liao, Tzu-Hung Chuang, Shih-Chuan Chiu, Yi-Nan Lee
  • Publication number: 20230375611
    Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj Mhala, Calvin Yi-Ping Chao
  • Patent number: 11754616
    Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj M. Mhala, Calvin Yi-Ping Chao
  • Publication number: 20230011763
    Abstract: The present application provides a gesture determining method and an electronic device. The gesture determining method includes: sensing a control gesture through at least one motion sensor, and correspondingly generating sensing data; sequentially segmenting the sensing data into a plurality of streaming windows according to a unit of time, each streaming window including a group of sensing values; determining whether a sensing value in a streaming window is greater than a critical value, and triggering subsequent gesture recognition when the sensing value is greater than the critical value; and performing a recognition operation on the streaming window by using a gesture recognition model to consecutively output a recognition result; and determining whether the recognition result meets an output condition, and outputting a predicted gesture corresponding to the recognition result when the recognition result meets the output condition.
    Type: Application
    Filed: June 20, 2022
    Publication date: January 12, 2023
    Inventors: Shih-Chieh Liao, Chin-Hao Chang, Shih-Chuan Chiu, Yi-Nan Lee, Chia-Hao Kang, Wei-Cheng Chen, Tzu-Hung Chuang
  • Publication number: 20220337206
    Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
  • Patent number: 11424726
    Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
  • Publication number: 20210373068
    Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj M. Mhala, Calvin Yi-Ping Chao
  • Publication number: 20210313940
    Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
  • Patent number: 11131894
    Abstract: A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N?3, Ma?2, Ma+Mb?N?1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is ?R, and 0<|?R|?10%.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 28, 2021
    Assignee: Au Optronics Corporation
    Inventors: Chin-Hao Chang, Wei-Li Lin
  • Publication number: 20210173272
    Abstract: A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N?3, Ma?2, Ma+Mb?N?1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is ?R, and 0<|?R|?10%.
    Type: Application
    Filed: June 29, 2020
    Publication date: June 10, 2021
    Applicant: Au Optronics Corporation
    Inventors: Chin-Hao Chang, Wei-Li Lin
  • Publication number: 20200030206
    Abstract: A nail polish composition system includes (a) a base coat nail polish composition including organic solvents, film-forming compounds, plasticizers, and one or more additives; and (b) a top coat nail polish composition including a mixture of cyanoacrylates and a methacrylate. The base coat nail polish composition is applied to a fingernail to form a base coat film. Thereafter, the top coat nail polish composition is applied on or over the base coat film to form a top coat film. The nail polish composition system can significantly shorten the time required for drying the base and top coat nail polish compositions. In addition, the nail polish composition system may be applied without dipping the fingernail in powder glaze.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 30, 2020
    Inventor: Chin Hao Chang
  • Patent number: 10537509
    Abstract: A nail glue composition contains Beta-methoxyethyl cyanoacrylate, octyl cyanoacrylate, and polymethyl methacrylate. The nail glue composition is substantially odorless and has increased softness.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: January 21, 2020
    Inventor: Chin Hao Chang
  • Publication number: 20190298628
    Abstract: A nail glue composition contains Beta-methoxyethyl cyanoacrylate, octyl cyanoacrylate, and polymethyl methacrylate. The nail glue composition is substantially odorless and has increased softness.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Inventor: Chin Hao Chang
  • Publication number: 20190281946
    Abstract: The present invention relates to a lamp for use in curing gel polish applied to nails, such as fingernails or toenails. The lamp includes a housing having an opening for receiving, at least, a part of a hand including one or more fingers or a part of a foot including one or more toes. The lamp also includes one or more retractable feet attached to a bottom of the housing adjacent a front end thereof for elevating the front end of the housing so as to facilitate the insertion or removal, or the proper positioning, of the part of the foot or the hand in or from the opening of the housing. The lamp also includes a bottom plate and a mechanically releasable mechanism for removably attaching the bottom plate to the bottom of the housing.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 19, 2019
    Inventors: Ryan Kim, Chin Hao Chang