Abstract: A new method of forming polysilicon resistors having differing resistances using a dual polysilicon process is described. A first polysilicon layer is deposited over a dielectric layer on a semiconductor substrate. The first polysilicon layer is etched away where it is not covered by a mask. Thereafter, a second polysilicon layer is deposited overlying the first polysilicon layer and the dielectric layer. The first and second polysilicon layers are patterned to form a first polysilicon structure comprising the first and second polysilicon layers over the dielectric layer and a second polysilicon structure comprising the second polysilicon layer overlying the dielectric layer. The first and second polysilicon structures are doped to form the first polysilicon structure having a first resistance and the second polysilicon structure having a second resistance wherein the first resistance is lower than the second resistance.

Abstract: A process has been developed in which photoresist thinning at the edges of silicon chips, resulting from photoresist flowing from semiconductor chips, exhibiting features with raised topographies, to flat scribe regions, has been reduced. The reduction in photoresist flowing has been accomplished by creating a chessboard pattern of raised insulator and metal features, in the scribe line region, thus reducing the differences in topography between the scribe line and chip regions. The areas between the raised mesas, in the scribe line regions, are used for laser or optical endpoint detection of RIE processes.