Patents by Inventor Chin Hock Toh
Chin Hock Toh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8586465Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.Type: GrantFiled: June 5, 2008Date of Patent: November 19, 2013Assignee: United Test and Assembly Center LtdInventors: Hao Liu, Yi Sheng Anthony Sun, Ravi Kanth Kolan, Chin Hock Toh
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Patent number: 8426246Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.Type: GrantFiled: February 21, 2012Date of Patent: April 23, 2013Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Hao Liu, Ravi Kanth Kolan
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Patent number: 8399985Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.Type: GrantFiled: September 25, 2011Date of Patent: March 19, 2013Assignee: United Test And Assembly Center Ltd.Inventors: Ravi Kanth Kolan, Hao Liu, Chin Hock Toh
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Patent number: 8384203Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.Type: GrantFiled: July 20, 2009Date of Patent: February 26, 2013Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Yi Sheng Anthony Sun, Xue Ren Zhang, Ravi Kanth Kolan
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Publication number: 20120193812Abstract: A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes a first surface and a second surface. The through interposer vias extend from the first surface to the second surface of the interposer. A first die is mounted on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer.Type: ApplicationFiled: January 29, 2012Publication date: August 2, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock TOH, Kriangsak Sae LE
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Publication number: 20120149150Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.Type: ApplicationFiled: February 21, 2012Publication date: June 14, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock TOH, Hao LIU, Ravi Kanth KOLAN
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Publication number: 20120104628Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.Type: ApplicationFiled: January 10, 2012Publication date: May 3, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock TOH, Yao Huang HUANG, Ravi Kanth KOLAN, Wei Liang YUAN, Susanto TANARY, Yi Sheng Anthony SUN
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Patent number: 8143719Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.Type: GrantFiled: June 5, 2008Date of Patent: March 27, 2012Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Hao Liu, Ravi Kanth Kolan
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Patent number: 8115292Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.Type: GrantFiled: October 23, 2009Date of Patent: February 14, 2012Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Yao Huang Huang, Ravi Kanth Kolan, Wei Liang Yuan, Susanto Tanary, Anthony Yi Sheng Sun
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Publication number: 20120018869Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.Type: ApplicationFiled: September 25, 2011Publication date: January 26, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Ravi Kanth KOLAN, Hao LIU, Chin Hock TOH
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Patent number: 8030761Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.Type: GrantFiled: May 23, 2008Date of Patent: October 4, 2011Assignee: United Test and Assembly Center Ltd.Inventors: Ravi Kanth Kolan, Hao Liu, Chin Hock Toh
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Patent number: 7948095Abstract: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.Type: GrantFiled: February 11, 2009Date of Patent: May 24, 2011Assignee: United Test and Assembly Center Ltd.Inventors: Catherine Bee Liang Ng, Chin Hock Toh, Anthony Yi-Sheng Sun
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Publication number: 20100261313Abstract: A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.Type: ApplicationFiled: April 13, 2010Publication date: October 14, 2010Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock TOH, Keng Yuen AU, Reynaldo Vincent Hernandez STA AGUEDA, Bee Liang Catherine NG, Librado Amurao GATBONTON, Xue Ren ZHANG, Yi-Sheng Anthony SUN
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Publication number: 20100109169Abstract: A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly.Type: ApplicationFiled: April 28, 2009Publication date: May 6, 2010Applicant: UNITED TEST AND ASSEMBLY CENTER LTDInventors: Ravi Kanth KOLAN, Anthony Yi-Sheng Sun, Chin Hock Toh, Catherine Bee Liang Ng, Xue Ren Zhang
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Publication number: 20100109142Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.Type: ApplicationFiled: October 23, 2009Publication date: May 6, 2010Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock Toh, Yao Huang Huang, Ravi Kanth Kolan, Wei Liang Yuan, Susanto Tanary, Yi Sheng Anthony Sun
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Publication number: 20100013081Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.Type: ApplicationFiled: July 20, 2009Publication date: January 21, 2010Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock TOH, Yi Sheng Anthony SUN, Xue Ren ZHANG, Ravi Kanth KOLAN
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Publication number: 20080303163Abstract: A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.Type: ApplicationFiled: June 5, 2008Publication date: December 11, 2008Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Hao LIU, Yi Sheng Anthony SUN, Ravi Kanth KOLAN, Chin Hock TOH
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Publication number: 20080303031Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.Type: ApplicationFiled: June 5, 2008Publication date: December 11, 2008Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chin Hock TOH, Hao LIU, Ravi Kanth KOLAN
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Publication number: 20080290505Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.Type: ApplicationFiled: May 23, 2008Publication date: November 27, 2008Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Ravi Kanth KOLAN, Hao LIU, Chin Hock TOH